upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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307 lines
8.4 KiB
307 lines
8.4 KiB
/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx35_pins.h>
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#include <asm/arch/iomux.h>
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#include <i2c.h>
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#include <fsl_pmic.h>
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#include <mc9sdz60.h>
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#include <mc13892.h>
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#include <linux/types.h>
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#include <asm/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <netdev.h>
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#ifndef CONFIG_BOARD_LATE_INIT
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#error "CONFIG_BOARD_LATE_INIT must be set for this board"
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#endif
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#ifndef CONFIG_BOARD_EARLY_INIT_F
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#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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u32 size1, size2;
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size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
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gd->ram_size = size1 + size2;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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}
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static void setup_iomux_i2c(void)
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{
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int pad;
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/* setup pins for I2C1 */
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mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
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mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
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pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
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| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
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mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
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mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
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}
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static void setup_iomux_spi(void)
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{
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mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
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mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
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mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
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mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
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mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
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}
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static void setup_iomux_fec(void)
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{
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int pad;
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/* setup pins for FEC */
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mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
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mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
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pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
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PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
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mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
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PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
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PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
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PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
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PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
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PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
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PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
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PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
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PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
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PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
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mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
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PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
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PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
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PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
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PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
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PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
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PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
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PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
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PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
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mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
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PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
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}
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int board_early_init_f(void)
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{
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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/* enable clocks */
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writel(readl(&ccm->cgr0) |
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MXC_CCM_CGR0_EMI_MASK |
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MXC_CCM_CGR0_EDI0_MASK |
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MXC_CCM_CGR0_EPIT1_MASK,
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&ccm->cgr0);
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writel(readl(&ccm->cgr1) |
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MXC_CCM_CGR1_FEC_MASK |
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MXC_CCM_CGR1_GPIO1_MASK |
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MXC_CCM_CGR1_GPIO2_MASK |
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MXC_CCM_CGR1_GPIO3_MASK |
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MXC_CCM_CGR1_I2C1_MASK |
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MXC_CCM_CGR1_I2C2_MASK |
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MXC_CCM_CGR1_IPU_MASK,
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&ccm->cgr1);
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/* Setup NAND */
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__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
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setup_iomux_i2c();
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setup_iomux_fec();
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setup_iomux_spi();
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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static inline int pmic_detect(void)
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{
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int id;
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id = pmic_reg_read(REG_IDENTIFICATION);
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id = (id >> 6) & 0x7;
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if (id == 0x7)
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return 1;
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return 0;
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}
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u32 get_board_rev(void)
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{
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int rev;
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rev = pmic_detect();
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return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
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}
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int board_late_init(void)
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{
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u8 val;
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u32 pmic_val;
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if (pmic_detect()) {
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mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
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MUX_CONFIG_ALT1);
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pmic_val = pmic_reg_read(REG_SETTING_0);
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pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V);
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pmic_val = pmic_reg_read(REG_MODE_0);
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pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN);
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mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
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mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
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gpio_direction_output(37, 1);
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}
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val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
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mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
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mdelay(200);
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val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
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mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
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mdelay(200);
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val |= 0x80;
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mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
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return 0;
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}
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int checkboard(void)
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{
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 cpu_rev = get_cpu_rev();
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/*
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* Be sure that I2C is initialized to check
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* the board revision
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*/
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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/* Print board revision */
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printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F);
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/* Print CPU revision */
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printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F);
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switch (readl(&ccm->rcsr) & 0x0F) {
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case 0x0000:
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puts("POR");
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break;
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case 0x0002:
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puts("JTAG");
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break;
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case 0x0004:
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puts("RST");
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break;
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case 0x0008:
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puts("WDT");
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break;
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default:
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puts("unknown");
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}
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puts("]\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = -ENODEV;
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#if defined(CONFIG_SMC911X)
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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cpu_eth_init(bis);
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return rc;
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}
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