upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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78 lines
2.2 KiB
78 lines
2.2 KiB
/*
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*
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* Functions for omap5 based boards.
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*
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* (C) Copyright 2011
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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* Sricharan <r.sricharan@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/sizes.h>
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#include <asm/utils.h>
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#include <asm/arch/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 *const omap5_revision = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
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static struct gpio_bank gpio_bank_54xx[6] = {
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{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
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};
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const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
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#ifdef CONFIG_SPL_BUILD
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/*
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* Some tuning of IOs for optimal power and performance
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*/
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void do_io_settings(void)
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{
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}
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#endif
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void init_omap_revision(void)
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{
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/*
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* For some of the ES2/ES1 boards ID_CODE is not reliable:
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* Also, ES1 and ES2 have different ARM revisions
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* So use ARM revision for identification
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*/
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unsigned int rev = cortex_rev();
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switch (rev) {
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case MIDR_CORTEX_A15_R0P0:
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*omap5_revision = OMAP5430_ES1_0;
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default:
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*omap5_revision = OMAP5430_SILICON_ID_INVALID;
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}
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}
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