upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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624 lines
18 KiB
624 lines
18 KiB
/*
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* (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
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*
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* (C) Copyright 2009-2010
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* Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/bitops.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mpc512x.h>
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#include <fdt_support.h>
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#include <flash.h>
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#ifdef CONFIG_MISC_INIT_R
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#include <i2c.h>
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#endif
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#include <serial.h>
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#include <jffs2/load_kernel.h>
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#include <mtd_node.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[];
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ulong flash_get_size (phys_addr_t base, int banknum);
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sdram_conf_t mddrc_config[] = {
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{
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(512 << 20), /* 512 MB RAM configuration */
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{
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CONFIG_SYS_MDDRC_SYS_CFG,
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CONFIG_SYS_MDDRC_TIME_CFG0,
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CONFIG_SYS_MDDRC_TIME_CFG1,
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CONFIG_SYS_MDDRC_TIME_CFG2
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}
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},
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{
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(128 << 20), /* 128 MB RAM configuration */
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{
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CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
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CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
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CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
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CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
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}
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},
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};
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phys_size_t initdram (int board_type)
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{
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int i;
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u32 msize = 0;
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u32 pdm360ng_init_seq[] = {
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_MICRON_INIT_DEV_OP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_EM2,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_EM2,
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CONFIG_SYS_DDRCMD_EM3,
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CONFIG_SYS_DDRCMD_EN_DLL,
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CONFIG_SYS_DDRCMD_RES_DLL,
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_MICRON_INIT_DEV_OP,
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CONFIG_SYS_DDRCMD_OCD_DEFAULT,
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CONFIG_SYS_DDRCMD_OCD_EXIT,
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_NOP
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};
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for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
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msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
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ARRAY_SIZE(pdm360ng_init_seq));
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if (msize == mddrc_config[i].size)
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break;
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}
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return msize;
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}
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static int set_lcd_brightness(char *);
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int misc_init_r(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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/*
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* Re-configure flash setup using auto-detected info
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*/
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if (flash_info[1].size > 0) {
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out_be32(&im->sysconf.lpcs1aw,
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CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
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CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
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flash_info[1].size));
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sync_law(&im->sysconf.lpcs1aw);
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/*
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* Re-check to get correct base address
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*/
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flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
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} else {
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/* Disable Bank 1 */
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out_be32(&im->sysconf.lpcs1aw, 0x01000100);
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sync_law(&im->sysconf.lpcs1aw);
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}
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out_be32(&im->sysconf.lpcs0aw,
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CSAW_START(gd->bd->bi_flashstart) |
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CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
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sync_law(&im->sysconf.lpcs0aw);
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/*
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* Re-check to get correct base address
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*/
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flash_get_size (gd->bd->bi_flashstart, 0);
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/*
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* Re-do flash protection upon new addresses
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*/
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flash_protect (FLAG_PROTECT_CLEAR,
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gd->bd->bi_flashstart, 0xffffffff,
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&flash_info[0]);
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/* Monitor protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
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&flash_info[0]);
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/* Environment protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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#ifdef CONFIG_ENV_ADDR_REDUND
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/* Redundant environment protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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#endif
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#ifdef CONFIG_FSL_DIU_FB
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set_lcd_brightness(0);
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/* Switch LCD-Backlight and LVDS-Interface on */
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setbits_be32(&im->gpio.gpdir, 0x01040000);
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clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
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#endif
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#if defined(CONFIG_HARD_I2C)
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if (!getenv("ethaddr")) {
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uchar buf[6];
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uchar ifm_oui[3] = { 0, 2, 1, };
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int ret;
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/* I2C-0 for on-board eeprom */
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i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
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/* Read ethaddr from EEPROM */
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
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CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
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if (ret != 0) {
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printf("Error: Unable to read MAC from I2C"
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" EEPROM at address %02X:%02X\n",
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CONFIG_SYS_I2C_EEPROM_ADDR,
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CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
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return 1;
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}
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/* Owned by IFM ? */
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if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
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printf("Illegal MAC address in EEPROM: %pM\n", buf);
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return 1;
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}
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eth_setenv_enetaddr("ethaddr", buf);
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}
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#endif /* defined(CONFIG_HARD_I2C) */
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return 0;
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}
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static iopin_t ioregs_init[] = {
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/* FUNC1=LPC_CS4 */
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{
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offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
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IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC3=GPIO10 */
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{
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offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* FUNC1=CAN3_TX */
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{
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offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* FUNC3=GPIO14 */
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{
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offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
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/* DIU_LD22-DIU_LD23 */
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{
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offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
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},
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/* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
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/* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
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{
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offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
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},
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/* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
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/* VIU_DATA0-VIU_DATA2 */
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{
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offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
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},
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/* FUNC2=FEC_TXD_0 */
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{
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offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
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},
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/* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
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/* VIU_DATA3, VIU_DATA4 */
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{
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offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
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},
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/* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
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/* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
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/* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
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{
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offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
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},
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/* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
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/* DIU_LD00-DIU_LD21 */
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{
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offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
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},
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/* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
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/* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
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{
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offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC2=CAN3_RX */
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{
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offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* Sets lowest slew on 2 CAN_TX Pins*/
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{
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offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
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IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
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/* CAN4_TX, CAN4_RX */
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{
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offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
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/* GPIO8, GPIO9 */
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{
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offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
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/* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
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{
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offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
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/* FEC_RXD_3, FEC_RXD_2 */
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{
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offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC3=GPIO17 */
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{
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offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
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/* GPIO2, GPIO20, GPIO21 */
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{
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offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* FUNC2=VIU_PIX_CLK */
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{
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offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
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/* GPIO24, GPIO25 */
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{
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offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* FUNC1=NFC_CE2 */
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{
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offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
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IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
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/* VIU_DATA5-VIU_DATA9 */
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{
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offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
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/* LPC_TSIZ1-LPC_TSIZ2 */
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{
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offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC1=LPC_TS */
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{
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offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC3=GPIO16 */
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{
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offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
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},
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/* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
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/* GPIO18-GPIO19, GPT7/GPIO7 */
|
|
{
|
|
offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
|
|
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
|
|
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
|
|
},
|
|
/* FUNC3=GPIO0/GPT0 */
|
|
{
|
|
offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
|
|
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
|
|
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
|
|
},
|
|
/* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
|
|
/* GPIO11, GPIO2, GPIO12, GPIO13 */
|
|
{
|
|
offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
|
|
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
|
|
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
|
|
},
|
|
/* FUNC2=DIU_DE */
|
|
{
|
|
offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
|
|
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
|
|
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
|
|
}
|
|
};
|
|
|
|
int checkboard (void)
|
|
{
|
|
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
|
|
|
puts("Board: PDM360NG\n");
|
|
|
|
/* initialize function mux & slew rate IO inter alia on IO Pins */
|
|
|
|
iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
|
|
|
|
/* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
|
|
setbits_be32(&im->io_ctrl.io_control_gp,
|
|
(1 << 0) | /* GP_MUX7->GPIO7 */
|
|
(1 << 5)); /* GP_MUX2->GPIO2 */
|
|
|
|
/* configure GPIO24 (VIU_CE), output/high */
|
|
setbits_be32(&im->gpio.gpdir, 0x80);
|
|
setbits_be32(&im->gpio.gpdat, 0x80);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
|
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
|
|
struct node_info nodes[] = {
|
|
{ "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
|
|
{ "cfi-flash", MTD_DEV_TYPE_NOR, },
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_VIDEO)
|
|
/*
|
|
* EDID block has been generated using Phoenix EDID Designer 1.3.
|
|
* This tool creates a text file containing:
|
|
*
|
|
* EDID BYTES:
|
|
* 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
|
|
* ------------------------------------------------
|
|
* 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
|
|
* 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
|
|
* 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
|
|
* 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
|
|
* 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
|
|
* 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
|
|
* 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
|
|
* 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
|
|
*
|
|
* Then this data has been manually converted to the char
|
|
* array below.
|
|
*/
|
|
static unsigned char edid_buf[128] = {
|
|
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
|
|
0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
|
|
0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
|
|
0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
|
|
0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
|
|
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
|
|
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
|
|
0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
|
|
0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
|
|
0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
|
|
0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
|
|
0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
|
|
0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
|
|
0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
|
|
0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
|
|
0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
|
|
};
|
|
#endif
|
|
|
|
void ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
u32 val[8];
|
|
int rc, i = 0;
|
|
|
|
ft_cpu_setup(blob, bd);
|
|
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
|
|
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
|
|
#endif
|
|
#if defined(CONFIG_VIDEO)
|
|
fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
|
|
#endif
|
|
|
|
/* Fixup NOR FLASH mapping */
|
|
val[i++] = 0; /* chip select number */
|
|
val[i++] = 0; /* always 0 */
|
|
val[i++] = gd->bd->bi_flashstart;
|
|
val[i++] = gd->bd->bi_flashsize;
|
|
|
|
/* Fixup MRAM mapping */
|
|
val[i++] = 2; /* chip select number */
|
|
val[i++] = 0; /* always 0 */
|
|
val[i++] = CONFIG_SYS_MRAM_BASE;
|
|
val[i++] = CONFIG_SYS_MRAM_SIZE;
|
|
|
|
rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
|
|
val, i * sizeof(u32), 1);
|
|
if (rc)
|
|
printf("Unable to update localbus ranges, err=%s\n",
|
|
fdt_strerror(rc));
|
|
|
|
/* Fixup reg property in NOR Flash node */
|
|
i = 0;
|
|
val[i++] = 0; /* always 0 */
|
|
val[i++] = 0; /* start at offset 0 */
|
|
val[i++] = flash_info[0].size; /* size of Bank 0 */
|
|
|
|
/* Second Bank available? */
|
|
if (flash_info[1].size > 0) {
|
|
val[i++] = 0; /* always 0 */
|
|
val[i++] = flash_info[0].size; /* offset of Bank 1 */
|
|
val[i++] = flash_info[1].size; /* size of Bank 1 */
|
|
}
|
|
|
|
rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
|
|
val, i * sizeof(u32), 1);
|
|
if (rc)
|
|
printf("Unable to update flash reg property, err=%s\n",
|
|
fdt_strerror(rc));
|
|
}
|
|
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
|
|
|
/*
|
|
* If argument is NULL, set the LCD brightness to the
|
|
* value from "brightness" environment variable. Set
|
|
* the LCD brightness to the value specified by the
|
|
* argument otherwise. Default brightness is zero.
|
|
*/
|
|
#define MAX_BRIGHTNESS 99
|
|
static int set_lcd_brightness(char *brightness)
|
|
{
|
|
struct stdio_dev *cop_port;
|
|
char *env;
|
|
char cmd_buf[20];
|
|
int val = 0;
|
|
int cs = 0;
|
|
int len, i;
|
|
|
|
if (brightness) {
|
|
val = simple_strtol(brightness, NULL, 10);
|
|
} else {
|
|
env = getenv("brightness");
|
|
if (env)
|
|
val = simple_strtol(env, NULL, 10);
|
|
}
|
|
|
|
if (val < 0)
|
|
val = 0;
|
|
|
|
if (val > MAX_BRIGHTNESS)
|
|
val = MAX_BRIGHTNESS;
|
|
|
|
sprintf(cmd_buf, "$SB;%04d;", val);
|
|
|
|
len = strlen(cmd_buf);
|
|
for (i = 1; i <= len; i++)
|
|
cs += cmd_buf[i];
|
|
|
|
cs = (~cs + 1) & 0xff;
|
|
sprintf(cmd_buf + len, "%02X\n", cs);
|
|
|
|
/* IO Coprocessor communication */
|
|
cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
|
|
if (!cop_port) {
|
|
printf("Error: Can't open IO Coprocessor port.\n");
|
|
return -1;
|
|
}
|
|
|
|
debug("%s: cmd: %s", __func__, cmd_buf);
|
|
write_port(cop_port, cmd_buf);
|
|
/*
|
|
* Wait for transmission and maybe response data
|
|
* before closing the port.
|
|
*/
|
|
udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
|
|
memset(cmd_buf, 0, sizeof(cmd_buf));
|
|
len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
|
|
if (len)
|
|
printf("Error: %s\n", cmd_buf);
|
|
|
|
close_port(4);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
|
|
int argc, char * const argv[])
|
|
{
|
|
if (argc < 2)
|
|
return cmd_usage(cmdtp);
|
|
|
|
return set_lcd_brightness(argv[1]);
|
|
}
|
|
|
|
U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
|
|
"set LCD brightness",
|
|
"<brightness> - set LCD backlight level to <brightness>.\n"
|
|
);
|
|
|