upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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798 lines
22 KiB
798 lines
22 KiB
/*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* AM437x GP EVM */
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/dts-v1/;
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#include "am4372.dtsi"
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#include <dt-bindings/pinctrl/am43xx.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "TI AM437x GP EVM";
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compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
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aliases {
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display0 = &lcd0;
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serial3 = &uart3;
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};
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chosen {
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stdout-path = &uart0;
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tick-timer = &timer2;
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};
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vmmcsd_fixed: fixedregulator-sd {
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compatible = "regulator-fixed";
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regulator-name = "vmmcsd_fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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};
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vtt_fixed: fixedregulator-vtt {
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compatible = "regulator-fixed";
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regulator-name = "vtt_fixed";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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regulator-always-on;
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regulator-boot-on;
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enable-active-high;
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gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
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};
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vmmcwl_fixed: fixedregulator-mmcwl {
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compatible = "regulator-fixed";
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regulator-name = "vmmcwl_fixed";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
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brightness-levels = <0 51 53 56 62 75 101 152 255>;
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default-brightness-level = <8>;
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};
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matrix_keypad: matrix_keypad@0 {
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compatible = "gpio-matrix-keypad";
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debounce-delay-ms = <5>;
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col-scan-delay-us = <2>;
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row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
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&gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
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&gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
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col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
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&gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
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linux,keymap = <0x00000201 /* P1 */
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0x00010202 /* P2 */
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0x01000067 /* UP */
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0x0101006a /* RIGHT */
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0x02000069 /* LEFT */
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0x0201006c>; /* DOWN */
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};
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lcd0: display {
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compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
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label = "lcd";
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_pins>;
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/*
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* SelLCDorHDMI, LOW to select HDMI. This is not really the
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* panel's enable GPIO, but we don't have HDMI driver support nor
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* support to switch between two displays, so using this gpio as
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* panel's enable should be safe.
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*/
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enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
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panel-timing {
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clock-frequency = <33000000>;
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hactive = <800>;
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vactive = <480>;
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hfront-porch = <210>;
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hback-porch = <16>;
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hsync-len = <30>;
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vback-porch = <10>;
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vfront-porch = <22>;
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vsync-len = <13>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <1>;
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};
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port {
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lcd_in: endpoint {
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remote-endpoint = <&dpi_out>;
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};
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};
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};
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/* fixed 12MHz oscillator */
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refclk: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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};
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&am43xx_pinmux {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&wlan_pins_default>;
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pinctrl-1 = <&wlan_pins_sleep>;
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i2c0_pins: i2c0_pins {
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pinctrl-single,pins = <
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0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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>;
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};
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i2c1_pins: i2c1_pins {
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pinctrl-single,pins = <
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0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
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0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
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>;
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};
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
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>;
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};
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ecap0_pins: backlight_pins {
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pinctrl-single,pins = <
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0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
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>;
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};
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pixcir_ts_pins: pixcir_ts_pins {
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pinctrl-single,pins = <
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0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
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>;
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};
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
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0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
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0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
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0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
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0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
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0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
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0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
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0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
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0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
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0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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/* Slave 1 reset value */
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0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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/* MDIO */
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0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
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0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
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>;
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};
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davinci_mdio_sleep: davinci_mdio_sleep {
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pinctrl-single,pins = <
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/* MDIO reset value */
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0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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>;
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};
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nand_flash_x8: nand_flash_x8 {
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pinctrl-single,pins = <
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0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
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0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
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0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
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0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
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0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
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0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
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0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
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0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
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0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
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0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
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>;
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};
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dss_pins: dss_pins {
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pinctrl-single,pins = <
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0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
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0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
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0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
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0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
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0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
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0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
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0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
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0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
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>;
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};
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lcd_pins: lcd_pins {
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pinctrl-single,pins = <
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/* GPIO 5_8 to select LCD / HDMI */
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0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
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>;
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};
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dcan0_default: dcan0_default_pins {
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pinctrl-single,pins = <
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0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
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0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
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>;
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};
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dcan1_default: dcan1_default_pins {
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pinctrl-single,pins = <
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0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
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0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
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>;
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};
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vpfe0_pins_default: vpfe0_pins_default {
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pinctrl-single,pins = <
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0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
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0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
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0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
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0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
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0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
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0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
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0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
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0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
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0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
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0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
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0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
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0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
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0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
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>;
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};
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vpfe0_pins_sleep: vpfe0_pins_sleep {
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pinctrl-single,pins = <
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0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
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0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
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0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
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0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
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0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
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0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
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0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
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0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
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0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
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0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
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0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
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0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
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0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
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>;
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};
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vpfe1_pins_default: vpfe1_pins_default {
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pinctrl-single,pins = <
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0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
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0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
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0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
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0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
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0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
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0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
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0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
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0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
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0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
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0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
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0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
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0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
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0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
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>;
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};
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vpfe1_pins_sleep: vpfe1_pins_sleep {
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pinctrl-single,pins = <
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0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
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0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
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0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
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0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
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0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
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0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
|
|
0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
|
|
0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
|
|
0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
|
|
0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
|
|
0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
|
|
0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
|
|
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
|
|
>;
|
|
};
|
|
|
|
mmc3_pins_default: pinmux_mmc3_pins_default {
|
|
pinctrl-single,pins = <
|
|
0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
|
|
0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
|
|
0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
|
|
0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
|
|
0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
|
|
0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
|
|
>;
|
|
};
|
|
|
|
mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
|
|
pinctrl-single,pins = <
|
|
0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
|
|
0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
|
|
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
|
|
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
|
|
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
|
|
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
|
|
>;
|
|
};
|
|
|
|
wlan_pins_default: pinmux_wlan_pins_default {
|
|
pinctrl-single,pins = <
|
|
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
|
|
0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
|
|
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
|
|
>;
|
|
};
|
|
|
|
wlan_pins_sleep: pinmux_wlan_pins_sleep {
|
|
pinctrl-single,pins = <
|
|
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
|
|
0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
|
|
0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
|
|
>;
|
|
};
|
|
|
|
uart3_pins: uart3_pins {
|
|
pinctrl-single,pins = <
|
|
0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
|
|
0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
|
|
0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
|
|
0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
|
|
>;
|
|
};
|
|
};
|
|
|
|
&i2c0 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
clock-frequency = <100000>;
|
|
|
|
tps65218: tps65218@24 {
|
|
reg = <0x24>;
|
|
compatible = "ti,tps65218";
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
dcdc1: regulator-dcdc1 {
|
|
compatible = "ti,tps65218-dcdc1";
|
|
regulator-name = "vdd_core";
|
|
regulator-min-microvolt = <912000>;
|
|
regulator-max-microvolt = <1144000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
dcdc2: regulator-dcdc2 {
|
|
compatible = "ti,tps65218-dcdc2";
|
|
regulator-name = "vdd_mpu";
|
|
regulator-min-microvolt = <912000>;
|
|
regulator-max-microvolt = <1378000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
dcdc3: regulator-dcdc3 {
|
|
compatible = "ti,tps65218-dcdc3";
|
|
regulator-name = "vdcdc3";
|
|
regulator-min-microvolt = <1500000>;
|
|
regulator-max-microvolt = <1500000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
dcdc5: regulator-dcdc5 {
|
|
compatible = "ti,tps65218-dcdc5";
|
|
regulator-name = "v1_0bat";
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
};
|
|
|
|
dcdc6: regulator-dcdc6 {
|
|
compatible = "ti,tps65218-dcdc6";
|
|
regulator-name = "v1_8bat";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo1: regulator-ldo1 {
|
|
compatible = "ti,tps65218-ldo1";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
|
|
ov2659@30 {
|
|
compatible = "ovti,ov2659";
|
|
reg = <0x30>;
|
|
|
|
clocks = <&refclk 0>;
|
|
clock-names = "xvclk";
|
|
|
|
port {
|
|
ov2659_0: endpoint {
|
|
remote-endpoint = <&vpfe1_ep>;
|
|
link-frequencies = /bits/ 64 <70000000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c1 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_pins>;
|
|
pixcir_ts@5c {
|
|
compatible = "pixcir,pixcir_tangoc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pixcir_ts_pins>;
|
|
reg = <0x5c>;
|
|
interrupt-parent = <&gpio3>;
|
|
interrupts = <22 0>;
|
|
|
|
attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
|
|
|
touchscreen-size-x = <1024>;
|
|
touchscreen-size-y = <600>;
|
|
};
|
|
|
|
ov2659@30 {
|
|
compatible = "ovti,ov2659";
|
|
reg = <0x30>;
|
|
|
|
clocks = <&refclk 0>;
|
|
clock-names = "xvclk";
|
|
|
|
port {
|
|
ov2659_1: endpoint {
|
|
remote-endpoint = <&vpfe0_ep>;
|
|
link-frequencies = /bits/ 64 <70000000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&epwmss0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&tscadc {
|
|
status = "okay";
|
|
|
|
adc {
|
|
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
|
};
|
|
};
|
|
|
|
&ecap0 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&ecap0_pins>;
|
|
};
|
|
|
|
&gpio0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio4 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio5 {
|
|
status = "okay";
|
|
ti,no-reset-on-init;
|
|
};
|
|
|
|
&mmc1 {
|
|
status = "okay";
|
|
vmmc-supply = <&vmmcsd_fixed>;
|
|
bus-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc1_pins>;
|
|
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
&mmc3 {
|
|
/* disable MMC3 as SDIO is not supported in U-Boot */
|
|
status = "disabled";
|
|
/* these are on the crossbar and are outlined in the
|
|
xbar-event-map element */
|
|
dmas = <&edma 30
|
|
&edma 31>;
|
|
dma-names = "tx", "rx";
|
|
vmmc-supply = <&vmmcwl_fixed>;
|
|
bus-width = <4>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&mmc3_pins_default>;
|
|
pinctrl-1 = <&mmc3_pins_sleep>;
|
|
cap-power-off-card;
|
|
keep-power-in-suspend;
|
|
ti,non-removable;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
wlcore: wlcore@0 {
|
|
compatible = "ti,wl1835";
|
|
reg = <2>;
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
&edma {
|
|
ti,edma-xbar-event-map = /bits/ 16 <1 30
|
|
2 31>;
|
|
};
|
|
|
|
&uart3 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3_pins>;
|
|
};
|
|
|
|
&usb2_phy1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb1 {
|
|
dr_mode = "peripheral";
|
|
status = "okay";
|
|
};
|
|
|
|
&usb2_phy2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb2 {
|
|
dr_mode = "host";
|
|
status = "okay";
|
|
};
|
|
|
|
&mac {
|
|
slaves = <1>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&cpsw_default>;
|
|
pinctrl-1 = <&cpsw_sleep>;
|
|
status = "okay";
|
|
};
|
|
|
|
&davinci_mdio {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
|
status = "okay";
|
|
};
|
|
|
|
&cpsw_emac0 {
|
|
phy_id = <&davinci_mdio>, <0>;
|
|
phy-mode = "rgmii";
|
|
};
|
|
|
|
&elm {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpmc {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&nand_flash_x8>;
|
|
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
|
nand@0,0 {
|
|
reg = <0 0 4>; /* device IO registers */
|
|
ti,nand-ecc-opt = "bch16";
|
|
ti,elm-id = <&elm>;
|
|
nand-bus-width = <8>;
|
|
gpmc,device-width = <1>;
|
|
gpmc,sync-clk-ps = <0>;
|
|
gpmc,cs-on-ns = <0>;
|
|
gpmc,cs-rd-off-ns = <40>;
|
|
gpmc,cs-wr-off-ns = <40>;
|
|
gpmc,adv-on-ns = <0>;
|
|
gpmc,adv-rd-off-ns = <25>;
|
|
gpmc,adv-wr-off-ns = <25>;
|
|
gpmc,we-on-ns = <0>;
|
|
gpmc,we-off-ns = <20>;
|
|
gpmc,oe-on-ns = <3>;
|
|
gpmc,oe-off-ns = <30>;
|
|
gpmc,access-ns = <30>;
|
|
gpmc,rd-cycle-ns = <40>;
|
|
gpmc,wr-cycle-ns = <40>;
|
|
gpmc,wait-pin = <0>;
|
|
gpmc,bus-turnaround-ns = <0>;
|
|
gpmc,cycle2cycle-delay-ns = <0>;
|
|
gpmc,clk-activation-ns = <0>;
|
|
gpmc,wait-monitoring-ns = <0>;
|
|
gpmc,wr-access-ns = <40>;
|
|
gpmc,wr-data-mux-bus-ns = <0>;
|
|
/* MTD partition table */
|
|
/* All SPL-* partitions are sized to minimal length
|
|
* which can be independently programmable. For
|
|
* NAND flash this is equal to size of erase-block */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
partition@0 {
|
|
label = "NAND.SPL";
|
|
reg = <0x00000000 0x00040000>;
|
|
};
|
|
partition@1 {
|
|
label = "NAND.SPL.backup1";
|
|
reg = <0x00040000 0x00040000>;
|
|
};
|
|
partition@2 {
|
|
label = "NAND.SPL.backup2";
|
|
reg = <0x00080000 0x00040000>;
|
|
};
|
|
partition@3 {
|
|
label = "NAND.SPL.backup3";
|
|
reg = <0x000c0000 0x00040000>;
|
|
};
|
|
partition@4 {
|
|
label = "NAND.u-boot-spl-os";
|
|
reg = <0x00100000 0x00080000>;
|
|
};
|
|
partition@5 {
|
|
label = "NAND.u-boot";
|
|
reg = <0x00180000 0x00100000>;
|
|
};
|
|
partition@6 {
|
|
label = "NAND.u-boot-env";
|
|
reg = <0x00280000 0x00040000>;
|
|
};
|
|
partition@7 {
|
|
label = "NAND.u-boot-env.backup1";
|
|
reg = <0x002c0000 0x00040000>;
|
|
};
|
|
partition@8 {
|
|
label = "NAND.kernel";
|
|
reg = <0x00300000 0x00700000>;
|
|
};
|
|
partition@9 {
|
|
label = "NAND.file-system";
|
|
reg = <0x00a00000 0x1f600000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&dss {
|
|
status = "ok";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&dss_pins>;
|
|
|
|
port {
|
|
dpi_out: endpoint@0 {
|
|
remote-endpoint = <&lcd_in>;
|
|
data-lines = <24>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&dcan0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&dcan0_default>;
|
|
status = "okay";
|
|
};
|
|
|
|
&dcan1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&dcan1_default>;
|
|
status = "okay";
|
|
};
|
|
|
|
&vpfe0 {
|
|
status = "okay";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&vpfe0_pins_default>;
|
|
pinctrl-1 = <&vpfe0_pins_sleep>;
|
|
|
|
port {
|
|
vpfe0_ep: endpoint {
|
|
remote-endpoint = <&ov2659_1>;
|
|
ti,am437x-vpfe-interface = <0>;
|
|
bus-width = <8>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&vpfe1 {
|
|
status = "okay";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&vpfe1_pins_default>;
|
|
pinctrl-1 = <&vpfe1_pins_sleep>;
|
|
|
|
port {
|
|
vpfe1_ep: endpoint {
|
|
remote-endpoint = <&ov2659_0>;
|
|
ti,am437x-vpfe-interface = <0>;
|
|
bus-width = <8>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
};
|
|
};
|
|
};
|
|
|