upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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254 lines
7.1 KiB
254 lines
7.1 KiB
/*
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* Copyright 2016 - Vikas Manocha <vikas.manocha@st.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "stm32f746.dtsi"
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#include <dt-bindings/memory/stm32-sdram.h>
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/ {
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model = "STMicroelectronics STM32F769-DISCO board";
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compatible = "st,stm32f769-disco", "st,stm32f7";
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chosen {
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bootargs = "root=/dev/ram rdinit=/linuxrc";
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stdout-path = "serial0:115200n8";
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};
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memory {
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reg = <0xC0000000 0x1000000>;
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};
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aliases {
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serial0 = &usart1;
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spi0 = &qspi;
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/* Aliases for gpios so as to use sequence */
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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};
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led1 {
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compatible = "st,led1";
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led-gpio = <&gpioj 5 0>;
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};
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button1 {
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compatible = "st,button1";
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button-gpio = <&gpioa 0 0>;
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};
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};
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&clk_hse {
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clock-frequency = <25000000>;
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};
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&pinctrl {
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usart1_pins_a: usart1@0 {
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pins1 {
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pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
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bias-disable;
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};
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};
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ethernet_mii: mii@0 {
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pins {
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pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
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<STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
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<STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
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<STM32F746_PA2_FUNC_ETH_MDIO>,
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<STM32F746_PC1_FUNC_ETH_MDC>,
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<STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
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<STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
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<STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
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<STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
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slew-rate = <2>;
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};
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};
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qspi_pins: qspi@0 {
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pins {
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pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
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<STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
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<STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>,
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<STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>,
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<STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
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<STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
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slew-rate = <2>;
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};
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};
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fmc_pins: fmc@0 {
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pins {
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pinmux = <STM32F746_PI10_FUNC_FMC_D31>,
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<STM32F746_PI9_FUNC_FMC_D30>,
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<STM32F746_PI7_FUNC_FMC_D29>,
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<STM32F746_PI6_FUNC_FMC_D28>,
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<STM32F746_PI3_FUNC_FMC_D27>,
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<STM32F746_PI2_FUNC_FMC_D26>,
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<STM32F746_PI1_FUNC_FMC_D25>,
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<STM32F746_PI0_FUNC_FMC_D24>,
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<STM32F746_PH15_FUNC_FMC_D23>,
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<STM32F746_PH14_FUNC_FMC_D22>,
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<STM32F746_PH13_FUNC_FMC_D21>,
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<STM32F746_PH12_FUNC_FMC_D20>,
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<STM32F746_PH11_FUNC_FMC_D19>,
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<STM32F746_PH10_FUNC_FMC_D18>,
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<STM32F746_PH9_FUNC_FMC_D17>,
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<STM32F746_PH8_FUNC_FMC_D16>,
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<STM32F746_PD10_FUNC_FMC_D15>,
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<STM32F746_PD9_FUNC_FMC_D14>,
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<STM32F746_PD8_FUNC_FMC_D13>,
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<STM32F746_PE15_FUNC_FMC_D12>,
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<STM32F746_PE14_FUNC_FMC_D11>,
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<STM32F746_PE13_FUNC_FMC_D10>,
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<STM32F746_PE12_FUNC_FMC_D9>,
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<STM32F746_PE11_FUNC_FMC_D8>,
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<STM32F746_PE10_FUNC_FMC_D7>,
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<STM32F746_PE9_FUNC_FMC_D6>,
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<STM32F746_PE8_FUNC_FMC_D5>,
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<STM32F746_PE7_FUNC_FMC_D4>,
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<STM32F746_PD1_FUNC_FMC_D3>,
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<STM32F746_PD0_FUNC_FMC_D2>,
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<STM32F746_PD15_FUNC_FMC_D1>,
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<STM32F746_PD14_FUNC_FMC_D0>,
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<STM32F746_PI5_FUNC_FMC_NBL3>,
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<STM32F746_PI4_FUNC_FMC_NBL2>,
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<STM32F746_PE1_FUNC_FMC_NBL1>,
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<STM32F746_PE0_FUNC_FMC_NBL0>,
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<STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
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<STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
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<STM32F746_PG1_FUNC_FMC_A11>,
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<STM32F746_PG0_FUNC_FMC_A10>,
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<STM32F746_PF15_FUNC_FMC_A9>,
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<STM32F746_PF14_FUNC_FMC_A8>,
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<STM32F746_PF13_FUNC_FMC_A7>,
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<STM32F746_PF12_FUNC_FMC_A6>,
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<STM32F746_PF5_FUNC_FMC_A5>,
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<STM32F746_PF4_FUNC_FMC_A4>,
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<STM32F746_PF3_FUNC_FMC_A3>,
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<STM32F746_PF2_FUNC_FMC_A2>,
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<STM32F746_PF1_FUNC_FMC_A1>,
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<STM32F746_PF0_FUNC_FMC_A0>,
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<STM32F746_PH3_FUNC_FMC_SDNE0>,
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<STM32F746_PH5_FUNC_FMC_SDNWE>,
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<STM32F746_PF11_FUNC_FMC_SDNRAS>,
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<STM32F746_PG15_FUNC_FMC_SDNCAS>,
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<STM32F746_PH2_FUNC_FMC_SDCKE0>,
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<STM32F746_PG8_FUNC_FMC_SDCLK>;
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slew-rate = <2>;
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};
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};
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};
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&usart1 {
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pinctrl-0 = <&usart1_pins_a>;
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pinctrl-names = "default";
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status = "okay";
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};
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&fmc {
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pinctrl-0 = <&fmc_pins>;
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pinctrl-names = "default";
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status = "okay";
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/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
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bank1: bank@0 {
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st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4
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CAS_3 SDCLK_2 RD_BURST_EN
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RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
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TRP_2 TRCD_2>;
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/* refcount = (64msec/total_row_sdram)*freq - 20 */
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st,sdram-refcount = < 1542 >;
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};
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};
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&mac {
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status = "okay";
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pinctrl-0 = <ðernet_mii>;
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phy-mode = "rmii";
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phy-handle = <&phy0>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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&qspi {
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pinctrl-0 = <&qspi_pins>;
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status = "okay";
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qflash0: n25q128a {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q128a13", "spi-flash";
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spi-max-frequency = <108000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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memory-map = <0x90000000 0x1000000>;
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reg = <0>;
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};
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};
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