upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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413 lines
10 KiB
413 lines
10 KiB
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/sizes.h>
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#include <asm/arch/at91sam9263.h>
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#include <asm/arch/at91sam9263_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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#include <lcd.h>
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#include <atmel_lcdc.h>
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#include <dataflash.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_CMD_NAND
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static void pm9263_nand_hw_init(void)
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{
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
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at91_sys_write(AT91_MATRIX_EBI0CSA,
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csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(1) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(1));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif
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#ifdef CONFIG_MACB
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static void pm9263_macb_hw_init(void)
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{
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/*
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* PB27 enables the 50MHz oscillator for Ethernet PHY
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* 1 - enable
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* 0 - disable
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*/
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at91_set_gpio_output(AT91_PIN_PB27, 1);
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at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
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/*
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* Disable pull-up on:
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* RXDV (PC25) => PHY normal mode (not Test mode)
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* ERX0 (PE25) => PHY ADDR0
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* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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writel(pin_to_mask(AT91_PIN_PC25),
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pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
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writel(pin_to_mask(AT91_PIN_PE25) |
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pin_to_mask(AT91_PIN_PE26),
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pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PC25),
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pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
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writel(pin_to_mask(AT91_PIN_PE25) |
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pin_to_mask(AT91_PIN_PE26),
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pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
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at91_macb_hw_init();
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}
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#endif
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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vl_col: 240,
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vl_row: 320,
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vl_clk: 4965000,
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vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
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ATMEL_LCDC_INVFRAME_INVERTED,
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vl_bpix: 3,
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vl_tft: 1,
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vl_hsync_len: 5,
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vl_left_margin: 1,
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vl_right_margin:33,
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vl_vsync_len: 1,
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vl_upper_margin:1,
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vl_lower_margin:0,
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mmio: AT91SAM9263_LCDC_BASE,
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};
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void lcd_enable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA22, 1); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
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}
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#ifdef CONFIG_LCD_IN_PSRAM
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#define PSRAM_CRE_PIN AT91_PIN_PB29
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#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
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/* Initialize the PSRAM memory */
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static int pm9263_lcd_hw_psram_init(void)
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{
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volatile uint16_t x;
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/* setup PB29 as output */
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at91_set_gpio_output(PSRAM_CRE_PIN, 1);
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at91_set_gpio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
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/* PSRAM: write BCR */
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x = readw(PSRAM_CTRL_REG);
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x = readw(PSRAM_CTRL_REG);
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writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
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writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
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/* write RCR of the PSRAM */
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x = readw(PSRAM_CTRL_REG);
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x = readw(PSRAM_CTRL_REG);
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writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
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/* set RCR; 0x10-async mode,0x90-page mode */
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writew(0x90, PSRAM_CTRL_REG);
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/*
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* test to see if the PSRAM is MT45W2M16A or MT45W2M16B
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* MT45W2M16B - CRE must be 0
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* MT45W2M16A - CRE must be 1
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*/
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writew(0x1234, PHYS_PSRAM);
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writew(0x5678, PHYS_PSRAM + 2);
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/* test if the chip is MT45W2M16B */
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if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
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/* try with CRE=1 (MT45W2M16A) */
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at91_set_gpio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
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/* write RCR of the PSRAM */
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x = readw(PSRAM_CTRL_REG);
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x = readw(PSRAM_CTRL_REG);
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writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
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/* set RCR;0x10-async mode,0x90-page mode */
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writew(0x90, PSRAM_CTRL_REG);
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writew(0x1234, PHYS_PSRAM);
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writew(0x5678, PHYS_PSRAM+2);
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if ((readw(PHYS_PSRAM) != 0x1234)
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|| (readw(PHYS_PSRAM + 2) != 0x5678))
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return 1;
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}
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/* Bus matrix */
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at91_sys_write( AT91_MATRIX_PRAS5, AT91_MATRIX_M5PR );
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at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY |
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(AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) |
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AT91_MATRIX_DEFMSTR_TYPE_FIXED |
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(AT91_MATRIX_SLOT_CYCLE & (0x80 << 0)));
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return 0;
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}
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#endif
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static void pm9263_lcd_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */
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at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
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at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
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at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
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at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
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at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
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at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
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at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
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at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
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at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
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at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
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at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
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at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
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at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
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at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
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at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
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at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
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at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
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at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
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at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
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at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
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at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
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at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
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/* Power Control */
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at91_set_gpio_output(AT91_PIN_PA22, 1);
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at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
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#ifdef CONFIG_LCD_IN_PSRAM
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/* initialize te PSRAM */
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int stat = pm9263_lcd_hw_psram_init();
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gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE;
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#else
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gd->fb_base = AT91SAM9263_SRAM0_BASE;
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#endif
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}
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#ifdef CONFIG_LCD_INFO
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#include <nand.h>
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#include <version.h>
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extern flash_info_t flash_info[];
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void lcd_show_board_info(void)
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{
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ulong dram_size, nand_size, flash_size, dataflash_size;
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int i;
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char temp[32];
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lcd_printf ("%s\n", U_BOOT_VERSION);
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lcd_printf ("(C) 2009 Ronetix GmbH\n");
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lcd_printf ("support@ronetix.at\n");
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lcd_printf ("%s CPU at %s MHz",
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AT91_CPU_NAME,
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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dram_size += gd->bd->bi_dram[i].size;
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nand_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_size += nand_info[i].size;
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flash_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
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flash_size += flash_info[i].size;
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dataflash_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
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dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
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dataflash_info[i].Device.pages_size;
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lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
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"4 MB PSRAM, %ld MB DataFlash\n",
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dram_size >> 20,
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nand_size >> 20,
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flash_size >> 20,
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dataflash_size >> 20);
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}
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#endif /* CONFIG_LCD_INFO */
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#endif /* CONFIG_LCD */
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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at91_sys_write(AT91_PMC_PCER,
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(1 << AT91SAM9263_ID_PIOA) |
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(1 << AT91SAM9263_ID_PIOCDE) |
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(1 << AT91SAM9263_ID_PIOB));
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/* arch number of AT91SAM9263EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_PM9263;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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at91_serial_hw_init();
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#ifdef CONFIG_CMD_NAND
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pm9263_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91_spi0_hw_init(1 << 0);
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#endif
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#ifdef CONFIG_MACB
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pm9263_macb_hw_init();
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#endif
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#ifdef CONFIG_USB_OHCI_NEW
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at91_uhp_hw_init();
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#endif
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#ifdef CONFIG_LCD
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pm9263_lcd_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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#ifdef CONFIG_MACB
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/*
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* Initialize ethernet HW addr prior to starting Linux,
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* needed for nfsroot
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*/
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eth_init(gd->bd);
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#endif
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x01);
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#endif
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return rc;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard (void)
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{
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char *ss;
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char buf[32];
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printf ("Board : Ronetix PM9263\n");
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printf ("Crystal frequency: %8s MHz\n",
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strmhz(buf, get_main_clk_rate()));
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printf ("CPU clock : %8s MHz\n",
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strmhz(buf, get_cpu_clk_rate()));
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printf ("Master clock : %8s MHz\n",
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strmhz(buf, get_mck_clk_rate()));
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switch (gd->fb_base) {
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case PHYS_PSRAM:
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ss = "(PSRAM)";
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break;
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case AT91SAM9263_SRAM0_BASE:
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ss = "(Internal SRAM)";
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break;
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default:
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ss = "";
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break;
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}
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printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
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printf ("\n");
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return 0;
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}
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#endif
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