upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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202 lines
6.9 KiB
202 lines
6.9 KiB
; General settings that can be overwritten in the host code
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; that calls the AISGen library.
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[General]
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; Can be 8 or 16 - used in emifa
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busWidth=8
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; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
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BootMode=UART
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; 8,16,24 - used for SPI,I2C
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;AddrWidth=8
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; NO_CRC,SECTION_CRC,SINGLE_CRC
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crcCheckType=NO_CRC
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; This section allows setting the PLL0 system clock with a
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; specified multiplier and divider as shown. The clock source
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; can also be chosen for internal or external.
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; |------24|------16|-------8|-------0|
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; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV|
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; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7|
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;[PLL0CONFIG]
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;PLL0CFG0 = 0x00180001
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;PLL0CFG1 = 0x00000205
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[PLLANDCLOCKCONFIG]
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PLL0CFG0 = 0x00180001
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PLL0CFG1 = 0x00000205
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PERIPHCLKCFG = 0x00000051
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; This section allows setting up the PLL1. Usually this will
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; take place as part of the EMIF3a DDR setup. The format of
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; the input args is as follows:
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; |------24|------16|-------8|-------0|
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; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
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; PLL1CFG1: | RSVD | PLLDIV3|
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[PLL1CONFIG]
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PLL1CFG0 = 0x18010001
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PLL1CFG1 = 0x00000002
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; This section lets us configure the peripheral interface
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; of the current booting peripheral (I2C, SPI, or UART).
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; Use with caution. The format of the PERIPHCLKCFG field
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; is as follows:
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; SPI: |------24|------16|-------8|-------0|
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; | RSVD |PRESCALE|
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;
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; I2C: |------24|------16|-------8|-------0|
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; | RSVD |PRESCALE| CLKL | CLKH |
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;
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; UART: |------24|------16|-------8|-------0|
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; | RSVD | OSR | DLH | DLL |
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[PERIPHCLKCFG]
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PERIPHCLKCFG = 0x00000051
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; This section can be used to configure the PLL1 and the EMIF3a registers
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; for starting the DDR2 interface.
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; See PLL1CONFIG section for the format of the PLL1CFG fields.
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; |------24|------16|-------8|-------0|
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; PLL1CFG0: | PLL1CFG |
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; PLL1CFG1: | PLL1CFG |
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; DDRPHYC1R: | DDRPHYC1R |
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; SDCR: | SDCR |
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; SDTIMR: | SDTIMR |
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; SDTIMR2: | SDTIMR2 |
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; SDRCR: | SDRCR |
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; CLK2XSRC: | CLK2XSRC |
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[EMIF3DDR]
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PLL1CFG0 = 0x18010001
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PLL1CFG1 = 0x00000002
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DDRPHYC1R = 0x000000C2
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SDCR = 0x0017C432
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SDTIMR = 0x26922A09
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SDTIMR2 = 0x4414C722
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SDRCR = 0x00000498
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CLK2XSRC = 0x00000000
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; This section can be used to configure the EMIFA to use
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; CS0 as an SDRAM interface. The fields required to do this
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; are given below.
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; |------24|------16|-------8|-------0|
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; SDBCR: | SDBCR |
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; SDTIMR: | SDTIMR |
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; SDRSRPDEXIT: | SDRSRPDEXIT |
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; SDRCR: | SDRCR |
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; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE |
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;[EMIF25SDRAM]
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;SDBCR = 0x00004421
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;SDTIMR = 0x42215810
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;SDRSRPDEXIT = 0x00000009
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;SDRCR = 0x00000410
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;DIV4p5_CLK_ENABLE = 0x00000001
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; This section can be used to configure the async chip selects
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; of the EMIFA (CS2-CS5). The fields required to do this
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; are given below.
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; |------24|------16|-------8|-------0|
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; A1CR: | A1CR |
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; A2CR: | A2CR |
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; A3CR: | A3CR |
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; A4CR: | A4CR |
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; NANDFCR: | NANDFCR |
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;[EMIF25ASYNC]
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;A1CR = 0x00000000
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;A2CR = 0x00000000
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;A3CR = 0x00000000
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;A4CR = 0x00000000
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;NANDFCR = 0x00000000
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[EMIF25ASYNC]
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A1CR = 0x00000000
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A2CR = 0x04202110
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A3CR = 0x00000000
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A4CR = 0x00000000
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NANDFCR = 0x00000012
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; This section should be used in place of PLL0CONFIG when
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; the I2C, SPI, or UART modes are being used. This ensures that
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; the system PLL and the peripheral's clocks are changed together.
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; See PLL0CONFIG section for the format of the PLL0CFG fields.
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; See PERIPHCLKCFG section for the format of the CLKCFG field.
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; |------24|------16|-------8|-------0|
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; PLL0CFG0: | PLL0CFG |
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; PLL0CFG1: | PLL0CFG |
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; PERIPHCLKCFG: | CLKCFG |
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;[PLLANDCLOCKCONFIG]
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;PLL0CFG0 = 0x00180001
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;PLL0CFG1 = 0x00000205
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;PERIPHCLKCFG = 0x00010032
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; This section should be used to setup the power state of modules
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; of the two PSCs. This section can be included multiple times to
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; allow the configuration of any or all of the device modules.
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; |------24|------16|-------8|-------0|
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; LPSCCFG: | PSCNUM | MODULE | PD | STATE |
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;[PSCCONFIG]
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;LPSCCFG=
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; This section allows setting of a single PINMUX register.
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; This section can be included multiple times to allow setting
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; as many PINMUX registers as needed.
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; |------24|------16|-------8|-------0|
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; REGNUM: | regNum |
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; MASK: | mask |
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; VALUE: | value |
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;[PINMUX]
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;REGNUM = 5
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;MASK = 0x00FF0000
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;VALUE = 0x00880000
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; No Params required - simply include this section for the fast boot
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; function to be called
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;[FASTBOOT]
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; This section allows setting up the PLL1. Usually this will
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; take place as part of the EMIF3a DDR setup. The format of
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; the input args is as follows:
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; |------24|------16|-------8|-------0|
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; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
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; PLL1CFG1: | RSVD | PLLDIV3|
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;[PLL1CONFIG]
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;PLL1CFG0 = 0x15010001
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;PLL1CFG1 = 0x00000002
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; This section can be used to configure the PLL1 and the EMIF3a registers
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; for starting the DDR2 interface on ARM-boot D800K002 devices.
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; |------24|------16|-------8|-------0|
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; DDRPHYC1R: | DDRPHYC1R |
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; SDCR: | SDCR |
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; SDTIMR: | SDTIMR |
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; SDTIMR2: | SDTIMR2 |
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; SDRCR: | SDRCR |
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; CLK2XSRC: | CLK2XSRC |
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;[ARM_EMIF3DDR_PATCHFXN]
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;DDRPHYC1R = 0x000000C2
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;SDCR = 0x0017C432
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;SDTIMR = 0x26922A09
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;SDTIMR2 = 0x4414C722
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;SDRCR = 0x00000498
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;CLK2XSRC = 0x00000000
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; This section can be used to configure the PLL1 and the EMIF3a registers
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; for starting the DDR2 interface on DSP-boot D800K002 devices.
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; |------24|------16|-------8|-------0|
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; DDRPHYC1R: | DDRPHYC1R |
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; SDCR: | SDCR |
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; SDTIMR: | SDTIMR |
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; SDTIMR2: | SDTIMR2 |
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; SDRCR: | SDRCR |
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; CLK2XSRC: | CLK2XSRC |
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;[DSP_EMIF3DDR_PATCHFXN]
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;DDRPHYC1R = 0x000000C4
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;SDCR = 0x08134632
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;SDTIMR = 0x26922A09
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;SDTIMR2 = 0x0014C722
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;SDRCR = 0x00000492
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;CLK2XSRC = 0x00000000
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;[INPUTFILE]
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;FILENAME=u-boot.bin
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;LOADADDRESS=0xC1080000
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;ENTRYPOINTADDRESS=0xC1080000
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