upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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534 lines
12 KiB
534 lines
12 KiB
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/ns_access.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ls102xa_stream_id.h>
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#include <asm/pcie_layerscape.h>
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#include <hwconfig.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <fsl_ifc.h>
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#include <fsl_sec.h>
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#include <spl.h>
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#include "../common/qixis.h"
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#include "ls1021aqds_qixis.h"
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#ifdef CONFIG_U_QE
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#include "../../../drivers/qe/qe.h"
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#endif
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#define PIN_MUX_SEL_CAN 0x03
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#define PIN_MUX_SEL_IIC2 0xa0
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#define PIN_MUX_SEL_RGMII 0x00
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#define PIN_MUX_SEL_SAI 0x0c
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#define PIN_MUX_SEL_SDHC 0x00
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#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
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#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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MUX_TYPE_CAN,
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MUX_TYPE_IIC2,
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MUX_TYPE_RGMII,
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MUX_TYPE_SAI,
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MUX_TYPE_SDHC,
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MUX_TYPE_SD_PCI4,
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MUX_TYPE_SD_PC_SA_SG_SG,
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MUX_TYPE_SD_PC_SA_PC_SG,
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MUX_TYPE_SD_PC_SG_SG,
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};
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int checkboard(void)
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{
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#ifndef CONFIG_QSPI_BOOT
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char buf[64];
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#endif
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#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
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u8 sw;
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#endif
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puts("Board: LS1021AQDS\n");
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#ifdef CONFIG_SD_BOOT
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puts("SD\n");
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#elif CONFIG_QSPI_BOOT
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puts("QSPI\n");
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#else
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank: %d\n", sw);
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else if (sw == 0x8)
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puts("PromJet\n");
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else if (sw == 0x9)
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puts("NAND\n");
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else if (sw == 0x15)
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printf("IFCCard\n");
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else
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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#endif
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#ifndef CONFIG_QSPI_BOOT
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printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
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QIXIS_READ(id), QIXIS_READ(arch));
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printf("FPGA: v%d (%s), build %d\n",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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#endif
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0f) {
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case QIXIS_SYSCLK_64:
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return 64000000;
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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int dram_init(void)
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{
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/*
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* When resuming from deep sleep, the I2C channel may not be
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* in the default channel. So, switch to the default channel
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* before accessing DDR SPD.
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*/
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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gd->ram_size = initdram(0);
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return 0;
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[1] = {
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{CONFIG_SYS_FSL_ESDHC_ADDR},
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};
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int board_mmc_init(bd_t *bis)
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{
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
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}
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#endif
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int board_early_init_f(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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#ifdef CONFIG_TSEC_ENET
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out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
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#endif
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#ifdef CONFIG_FSL_IFC
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init_early_memctl_regs();
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#endif
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#ifdef CONFIG_FSL_QSPI
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out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
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#endif
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/* Workaround for the issue that DDR could not respond to
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* barrier transaction which is generated by executing DSB/ISB
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* instruction. Set CCI-400 control override register to
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* terminate the barrier transaction. After DDR is initialized,
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* allow barrier transaction to DDR again */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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#ifdef CONFIG_NAND_BOOT
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 porsr1, pinctl;
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/*
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* There is LS1 SoC issue where NOR, FPGA are inaccessible during
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* NAND boot because IFC signals > IFC_AD7 are not enabled.
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* This workaround changes RCW source to make all signals enabled.
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*/
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porsr1 = in_be32(&gur->porsr1);
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pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
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DCFG_CCSR_PORSR1_RCW_SRC_I2C);
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out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
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pinctl);
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#endif
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/* Set global data pointer */
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gd = &gdata;
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/* Clear the BSS */
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memset(__bss_start, 0, __bss_end - __bss_start);
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#ifdef CONFIG_FSL_IFC
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init_early_memctl_regs();
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#endif
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get_clocks();
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preloader_console_init();
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#ifdef CONFIG_SPL_I2C_SUPPORT
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i2c_init_all();
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#endif
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
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dram_init();
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board_init_r(NULL, 0);
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}
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#endif
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int config_board_mux(int ctrl_type)
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{
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u8 reg12, reg14;
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reg12 = QIXIS_READ(brdcfg[12]);
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reg14 = QIXIS_READ(brdcfg[14]);
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switch (ctrl_type) {
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case MUX_TYPE_CAN:
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reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
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break;
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case MUX_TYPE_IIC2:
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reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
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break;
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case MUX_TYPE_RGMII:
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reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
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break;
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case MUX_TYPE_SAI:
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reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
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break;
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case MUX_TYPE_SDHC:
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reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
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break;
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case MUX_TYPE_SD_PCI4:
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reg12 = 0x38;
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break;
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case MUX_TYPE_SD_PC_SA_SG_SG:
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reg12 = 0x01;
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break;
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case MUX_TYPE_SD_PC_SA_PC_SG:
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reg12 = 0x01;
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break;
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case MUX_TYPE_SD_PC_SG_SG:
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reg12 = 0x21;
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break;
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default:
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printf("Wrong mux interface type\n");
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return -1;
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}
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QIXIS_WRITE(brdcfg[12], reg12);
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QIXIS_WRITE(brdcfg[14], reg14);
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return 0;
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}
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int config_serdes_mux(void)
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{
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struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 cfg;
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cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
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cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
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switch (cfg) {
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case 0x0:
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config_board_mux(MUX_TYPE_SD_PCI4);
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break;
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case 0x30:
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config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
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break;
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case 0x60:
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config_board_mux(MUX_TYPE_SD_PC_SG_SG);
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break;
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case 0x70:
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config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
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break;
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default:
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printf("SRDS1 prtcl:0x%x\n", cfg);
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break;
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}
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return 0;
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}
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int misc_init_r(void)
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{
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int conflict_flag;
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/* some signals can not enable simultaneous*/
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conflict_flag = 0;
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if (hwconfig("sdhc"))
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conflict_flag++;
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if (hwconfig("iic2"))
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conflict_flag++;
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if (conflict_flag > 1) {
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printf("WARNING: pin conflict !\n");
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return 0;
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}
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conflict_flag = 0;
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if (hwconfig("rgmii"))
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conflict_flag++;
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if (hwconfig("can"))
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conflict_flag++;
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if (hwconfig("sai"))
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conflict_flag++;
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if (conflict_flag > 1) {
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printf("WARNING: pin conflict !\n");
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return 0;
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}
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if (hwconfig("can"))
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config_board_mux(MUX_TYPE_CAN);
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else if (hwconfig("rgmii"))
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config_board_mux(MUX_TYPE_RGMII);
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else if (hwconfig("sai"))
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config_board_mux(MUX_TYPE_SAI);
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if (hwconfig("iic2"))
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config_board_mux(MUX_TYPE_IIC2);
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else if (hwconfig("sdhc"))
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config_board_mux(MUX_TYPE_SDHC);
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#ifdef CONFIG_FSL_CAAM
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return sec_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_LS102XA_NS_ACCESS
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static struct csu_ns_dev ns_dev[] = {
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{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
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{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
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{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
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{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
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{ CSU_CSLX_OCRAM, CSU_ALL_RW },
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{ CSU_CSLX_GIC, CSU_ALL_RW },
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{ CSU_CSLX_PCIE1, CSU_ALL_RW },
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{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
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{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
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{ CSU_CSLX_PCIE2, CSU_ALL_RW },
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{ CSU_CSLX_SATA, CSU_ALL_RW },
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{ CSU_CSLX_USB3, CSU_ALL_RW },
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{ CSU_CSLX_SERDES, CSU_ALL_RW },
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{ CSU_CSLX_QDMA, CSU_ALL_RW },
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{ CSU_CSLX_LPUART2, CSU_ALL_RW },
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{ CSU_CSLX_LPUART1, CSU_ALL_RW },
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{ CSU_CSLX_LPUART4, CSU_ALL_RW },
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{ CSU_CSLX_LPUART3, CSU_ALL_RW },
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{ CSU_CSLX_LPUART6, CSU_ALL_RW },
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{ CSU_CSLX_LPUART5, CSU_ALL_RW },
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{ CSU_CSLX_DSPI2, CSU_ALL_RW },
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{ CSU_CSLX_DSPI1, CSU_ALL_RW },
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{ CSU_CSLX_QSPI, CSU_ALL_RW },
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{ CSU_CSLX_ESDHC, CSU_ALL_RW },
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{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
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{ CSU_CSLX_IFC, CSU_ALL_RW },
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{ CSU_CSLX_I2C1, CSU_ALL_RW },
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{ CSU_CSLX_USB2, CSU_ALL_RW },
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{ CSU_CSLX_I2C3, CSU_ALL_RW },
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{ CSU_CSLX_I2C2, CSU_ALL_RW },
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{ CSU_CSLX_DUART2, CSU_ALL_RW },
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{ CSU_CSLX_DUART1, CSU_ALL_RW },
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{ CSU_CSLX_WDT2, CSU_ALL_RW },
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{ CSU_CSLX_WDT1, CSU_ALL_RW },
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{ CSU_CSLX_EDMA, CSU_ALL_RW },
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{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
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{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
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{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
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{ CSU_CSLX_DDR, CSU_ALL_RW },
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{ CSU_CSLX_QUICC, CSU_ALL_RW },
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{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
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{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
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{ CSU_CSLX_SFP, CSU_ALL_RW },
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{ CSU_CSLX_TMU, CSU_ALL_RW },
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{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
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{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
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{ CSU_CSLX_GPIO2, CSU_ALL_RW },
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{ CSU_CSLX_GPIO1, CSU_ALL_RW },
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{ CSU_CSLX_GPIO4, CSU_ALL_RW },
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{ CSU_CSLX_GPIO3, CSU_ALL_RW },
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{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
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{ CSU_CSLX_CSU, CSU_ALL_RW },
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{ CSU_CSLX_ASRC, CSU_ALL_RW },
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{ CSU_CSLX_SPDIF, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
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{ CSU_CSLX_SAI2, CSU_ALL_RW },
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{ CSU_CSLX_SAI1, CSU_ALL_RW },
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{ CSU_CSLX_SAI4, CSU_ALL_RW },
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{ CSU_CSLX_SAI3, CSU_ALL_RW },
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{ CSU_CSLX_FTM2, CSU_ALL_RW },
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{ CSU_CSLX_FTM1, CSU_ALL_RW },
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{ CSU_CSLX_FTM4, CSU_ALL_RW },
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{ CSU_CSLX_FTM3, CSU_ALL_RW },
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{ CSU_CSLX_FTM6, CSU_ALL_RW },
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{ CSU_CSLX_FTM5, CSU_ALL_RW },
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{ CSU_CSLX_FTM8, CSU_ALL_RW },
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{ CSU_CSLX_FTM7, CSU_ALL_RW },
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{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
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{ CSU_CSLX_EPU, CSU_ALL_RW },
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{ CSU_CSLX_GDI, CSU_ALL_RW },
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{ CSU_CSLX_DDI, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
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{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
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};
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#endif
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struct smmu_stream_id dev_stream_id[] = {
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{ 0x100, 0x01, "ETSEC MAC1" },
|
|
{ 0x104, 0x02, "ETSEC MAC2" },
|
|
{ 0x108, 0x03, "ETSEC MAC3" },
|
|
{ 0x10c, 0x04, "PEX1" },
|
|
{ 0x110, 0x05, "PEX2" },
|
|
{ 0x114, 0x06, "qDMA" },
|
|
{ 0x118, 0x07, "SATA" },
|
|
{ 0x11c, 0x08, "USB3" },
|
|
{ 0x120, 0x09, "QE" },
|
|
{ 0x124, 0x0a, "eSDHC" },
|
|
{ 0x128, 0x0b, "eMA" },
|
|
{ 0x14c, 0x0c, "2D-ACE" },
|
|
{ 0x150, 0x0d, "USB2" },
|
|
{ 0x18c, 0x0e, "DEBUG" },
|
|
};
|
|
|
|
int board_init(void)
|
|
{
|
|
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
|
|
|
|
/* Set CCI-400 control override register to
|
|
* enable barrier transaction */
|
|
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
|
|
/*
|
|
* Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
|
|
* All transactions are treated as non-shareable
|
|
*/
|
|
out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
|
|
out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
|
|
out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
|
|
|
|
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
|
|
|
#ifndef CONFIG_SYS_FSL_NO_SERDES
|
|
fsl_serdes_init();
|
|
config_serdes_mux();
|
|
#endif
|
|
|
|
ls102xa_config_smmu_stream_id(dev_stream_id,
|
|
ARRAY_SIZE(dev_stream_id));
|
|
|
|
#ifdef CONFIG_LS102XA_NS_ACCESS
|
|
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
|
|
#endif
|
|
|
|
#ifdef CONFIG_U_QE
|
|
u_qe_init();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
#ifdef CONFIG_PCIE_LAYERSCAPE
|
|
ft_pcie_setup(blob, bd);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
u8 flash_read8(void *addr)
|
|
{
|
|
return __raw_readb(addr + 1);
|
|
}
|
|
|
|
void flash_write16(u16 val, void *addr)
|
|
{
|
|
u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
|
|
|
|
__raw_writew(shftval, addr);
|
|
}
|
|
|
|
u16 flash_read16(void *addr)
|
|
{
|
|
u16 val = __raw_readw(addr);
|
|
|
|
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
|
|
}
|
|
|