upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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129 lines
2.8 KiB
129 lines
2.8 KiB
/*
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* Copyright (C) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <pch.h>
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#include <asm/lapic.h>
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#include <asm/pci.h>
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#include <asm/arch/bd82x6x.h>
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#include <asm/arch/model_206ax.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/sandybridge.h>
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#define BIOS_CTRL 0xdc
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static int bd82x6x_probe(struct udevice *dev)
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{
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const void *blob = gd->fdt_blob;
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struct pci_controller *hose;
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int sata_node, gma_node;
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int ret;
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if (!(gd->flags & GD_FLG_RELOC))
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return 0;
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hose = pci_bus_to_hose(0);
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lpc_enable(PCH_LPC_DEV);
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lpc_init_extra(hose, PCH_LPC_DEV);
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sata_node = fdtdec_next_compatible(blob, 0,
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COMPAT_INTEL_PANTHERPOINT_AHCI);
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if (sata_node < 0) {
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debug("%s: Cannot find SATA node\n", __func__);
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return -EINVAL;
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}
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bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
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bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
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bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
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gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
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if (gma_node < 0) {
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debug("%s: Cannot find GMA node\n", __func__);
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return -EINVAL;
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}
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ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev);
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if (ret)
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return ret;
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ret = gma_func0_init(dev, blob, gma_node);
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if (ret)
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return ret;
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return 0;
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}
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/* TODO(sjg@chromium.org): Move this to the PCH init() method */
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int bd82x6x_init_extra(void)
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{
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const void *blob = gd->fdt_blob;
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int sata_node;
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sata_node = fdtdec_next_compatible(blob, 0,
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COMPAT_INTEL_PANTHERPOINT_AHCI);
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if (sata_node < 0) {
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debug("%s: Cannot find SATA node\n", __func__);
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return -EINVAL;
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}
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bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
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return 0;
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}
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static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
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{
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u32 rcba;
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dm_pci_read_config32(dev, PCH_RCBA, &rcba);
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/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
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rcba = rcba & 0xffffc000;
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*sbasep = rcba + 0x3800;
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return 0;
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}
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static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
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{
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return PCHV_9;
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}
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static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
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{
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uint8_t bios_cntl;
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/* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
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dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
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if (protect) {
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bios_cntl &= ~BIOS_CTRL_BIOSWE;
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bios_cntl |= BIT(5);
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} else {
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bios_cntl |= BIOS_CTRL_BIOSWE;
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bios_cntl &= ~BIT(5);
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}
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dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
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return 0;
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}
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static const struct pch_ops bd82x6x_pch_ops = {
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.get_sbase = bd82x6x_pch_get_sbase,
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.get_version = bd82x6x_pch_get_version,
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.set_spi_protect = bd82x6x_set_spi_protect,
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};
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static const struct udevice_id bd82x6x_ids[] = {
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{ .compatible = "intel,bd82x6x" },
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{ }
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};
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U_BOOT_DRIVER(bd82x6x_drv) = {
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.name = "bd82x6x",
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.id = UCLASS_PCH,
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.of_match = bd82x6x_ids,
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.probe = bd82x6x_probe,
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.ops = &bd82x6x_pch_ops,
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};
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