upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Kumar Gala a09b9b68d4 powerpc/8xxx: Refactor SRIO initialization into common code ... Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>		14 years ago
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ddr	MPC8xxx DDR: align informational prints	14 years ago
Makefile	powerpc/8xxx: Refactor SRIO initialization into common code	14 years ago
cpu.c	…
fdt.c	powerpc/8xxx: Refactor SRIO initialization into common code	14 years ago
fsl_lbc.c	mpc85xx: rename sdram_init() lbc_sdram_init()	14 years ago
srio.c	powerpc/8xxx: Refactor SRIO initialization into common code	14 years ago