upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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294 lines
7.3 KiB
294 lines
7.3 KiB
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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#ifdef CONFIG_SYS_DDR_RAW_TIMING
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#if defined(CONFIG_P1020RDB_PROTO) || \
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defined(CONFIG_P1021RDB) || \
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defined(CONFIG_P1020UTM)
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/* Micron MT41J256M8_187E */
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 1073741824u,
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.capacity = 1073741824u,
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.primary_sdram_width = 32,
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.ec_sdram_width = 0,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 0,
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.burst_lengths_bitmask = 0x0c,
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.tCKmin_X_ps = 1870,
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.caslat_X = 0x1e << 4, /* 5,6,7,8 */
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.tAA_ps = 13125,
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.tWR_ps = 15000,
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.tRCD_ps = 13125,
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.tRRD_ps = 7500,
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.tRP_ps = 13125,
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.tRAS_ps = 37500,
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.tRC_ps = 50625,
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.tRFC_ps = 160000,
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.tWTR_ps = 7500,
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.tRTP_ps = 7500,
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.refresh_rate_ps = 7800000,
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.tFAW_ps = 37500,
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};
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#elif defined(CONFIG_P2020RDB)
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/* Micron MT41J128M16_15E */
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 1073741824u,
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.capacity = 1073741824u,
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.primary_sdram_width = 64,
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.ec_sdram_width = 0,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 14,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 0,
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.burst_lengths_bitmask = 0x0c,
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.tCKmin_X_ps = 1500,
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.caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */
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.tAA_ps = 13500,
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.tWR_ps = 15000,
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.tRCD_ps = 13500,
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.tRRD_ps = 6000,
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.tRP_ps = 13500,
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.tRAS_ps = 36000,
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.tRC_ps = 49500,
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.tRFC_ps = 160000,
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.tWTR_ps = 7500,
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.tRTP_ps = 7500,
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.refresh_rate_ps = 7800000,
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.tFAW_ps = 30000,
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};
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#elif defined(CONFIG_P1020MBG)
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/* Micron MT41J512M8_187E */
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 2,
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.rank_density = 1073741824u,
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.capacity = 2147483648u,
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.primary_sdram_width = 32,
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.ec_sdram_width = 0,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 0,
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.burst_lengths_bitmask = 0x0c,
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.tCKmin_X_ps = 1870,
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.caslat_X = 0x1e << 4, /* 5,6,7,8 */
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.tAA_ps = 13125,
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.tWR_ps = 15000,
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.tRCD_ps = 13125,
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.tRRD_ps = 7500,
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.tRP_ps = 13125,
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.tRAS_ps = 37500,
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.tRC_ps = 50625,
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.tRFC_ps = 160000,
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.tWTR_ps = 7500,
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.tRTP_ps = 7500,
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.refresh_rate_ps = 7800000,
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.tFAW_ps = 37500,
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};
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#elif defined(CONFIG_P1020RDB)
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/*
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* Samsung K4B2G0846C-HCF8
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* The following timing are for "downshift"
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* i.e. to use CL9 part as CL7
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* otherwise, tAA, tRCD, tRP will be 13500ps
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* and tRC will be 49500ps
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*/
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 1073741824u,
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.capacity = 1073741824u,
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.primary_sdram_width = 32,
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.ec_sdram_width = 0,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 0,
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.burst_lengths_bitmask = 0x0c,
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.tCKmin_X_ps = 1875,
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.caslat_X = 0x1e << 4, /* 5,6,7,8 */
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.tAA_ps = 13125,
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.tWR_ps = 15000,
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.tRCD_ps = 13125,
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.tRRD_ps = 7500,
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.tRP_ps = 13125,
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.tRAS_ps = 37500,
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.tRC_ps = 50625,
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.tRFC_ps = 160000,
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.tWTR_ps = 7500,
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.tRTP_ps = 7500,
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.refresh_rate_ps = 7800000,
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.tFAW_ps = 37500,
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};
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#elif defined(CONFIG_P1024RDB) || \
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defined(CONFIG_P1025RDB)
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/*
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* Samsung K4B2G0846C-HCH9
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* The following timing are for "downshift"
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* i.e. to use CL9 part as CL7
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* otherwise, tAA, tRCD, tRP will be 13500ps
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* and tRC will be 49500ps
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*/
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 1073741824u,
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.capacity = 1073741824u,
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.primary_sdram_width = 32,
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.ec_sdram_width = 0,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 0,
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.burst_lengths_bitmask = 0x0c,
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.tCKmin_X_ps = 1500,
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.caslat_X = 0x3e << 4, /* 5,6,7,8,9 */
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.tAA_ps = 13125,
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.tWR_ps = 15000,
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.tRCD_ps = 13125,
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.tRRD_ps = 6000,
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.tRP_ps = 13125,
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.tRAS_ps = 36000,
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.tRC_ps = 49125,
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.tRFC_ps = 160000,
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.tWTR_ps = 7500,
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.tRTP_ps = 7500,
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.refresh_rate_ps = 7800000,
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.tFAW_ps = 30000,
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};
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#else
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#error Missing raw timing data for this board
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#endif
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int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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unsigned int controller_number,
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unsigned int dimm_number)
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{
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const char dimm_model[] = "Fixed DDR on board";
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if ((controller_number == 0) && (dimm_number == 0)) {
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memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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}
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return 0;
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}
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#endif /* CONFIG_SYS_DDR_RAW_TIMING */
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#ifdef CONFIG_SYS_DDR_CS0_BNDS
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/* Fixed sdram init -- doesn't use serial presence detect. */
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phys_size_t fixed_sdram(void)
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{
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sys_info_t sysinfo;
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char buf[32];
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size_t ddr_size;
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fsl_ddr_cfg_regs_t ddr_cfg_regs = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
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.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
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.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
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#endif
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
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.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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get_sys_info(&sysinfo);
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, sysinfo.freqDDRBus));
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ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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};
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return ddr_size;
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}
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#endif
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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int i;
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popts->clk_adjust = 6;
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popts->cpo_override = 0x1f;
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popts->write_data_delay = 2;
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popts->half_strength_driver_enable = 1;
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/* Write leveling override */
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popts->wrlvl_en = 1;
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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popts->wrlvl_start = 0x8;
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popts->trwt_override = 1;
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popts->trwt = 0;
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if (pdimm->primary_sdram_width == 64)
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popts->data_bus_width = 0;
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else if (pdimm->primary_sdram_width == 32)
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popts->data_bus_width = 1;
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else
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printf("Error in DDR bus width configuration!\n");
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
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popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
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}
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}
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