upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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519 lines
13 KiB
519 lines
13 KiB
/*
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* Copyright (C) 2009 Freescale Semiconductor, Inc.
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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* Copyright (C) 2009-2012 Genesi USA, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx51.h>
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#include <asm/gpio.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <power/pmic.h>
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#include <fsl_pmic.h>
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#include <mc13892.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Compile-time error checking
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*/
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#ifndef CONFIG_MXC_SPI
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#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
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#endif
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/*
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* Board revisions
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*
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* Note that we get these revisions here for convenience, but we only set
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* up for the production model Smarttop (1.3) and Smartbook (2.0).
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*
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*/
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#define EFIKAMX_BOARD_REV_11 0x1
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#define EFIKAMX_BOARD_REV_12 0x2
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#define EFIKAMX_BOARD_REV_13 0x3
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#define EFIKAMX_BOARD_REV_14 0x4
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#define EFIKASB_BOARD_REV_13 0x1
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#define EFIKASB_BOARD_REV_20 0x2
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/*
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* Board identification
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*/
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static u32 get_mx_rev(void)
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{
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u32 rev = 0;
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/*
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* Retrieve board ID:
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*
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* gpio: 16 17 11
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* ==============
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* r1.1: 1+ 1 1
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* r1.2: 1 1 0
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* r1.3: 1 0 1
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* r1.4: 1 0 0
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*
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* + note: r1.1 does not strap this pin properly so it needs to
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* be hacked or ignored.
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*/
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/* set to 1 in order to get correct value on board rev 1.1 */
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gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
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gpio_direction_input(IMX_GPIO_NR(3, 11));
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gpio_direction_input(IMX_GPIO_NR(3, 16));
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gpio_direction_input(IMX_GPIO_NR(3, 17));
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rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
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rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
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rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
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return (~rev & 0x7) + 1;
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}
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static iomux_v3_cfg_t const efikasb_revision_pads[] = {
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MX51_PAD_EIM_CS3__GPIO2_28,
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MX51_PAD_EIM_CS4__GPIO2_29,
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};
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static inline u32 get_sb_rev(void)
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{
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u32 rev = 0;
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imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
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ARRAY_SIZE(efikasb_revision_pads));
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gpio_direction_input(IMX_GPIO_NR(2, 28));
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gpio_direction_input(IMX_GPIO_NR(2, 29));
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rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
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rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
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return rev;
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}
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inline uint32_t get_efikamx_rev(void)
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{
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if (machine_is_efikamx())
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return get_mx_rev();
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else if (machine_is_efikasb())
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return get_sb_rev();
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}
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u32 get_board_rev(void)
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{
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return get_cpu_rev() | (get_efikamx_rev() << 8);
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}
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/*
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* DRAM initialization
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*/
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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/*
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* UART configuration
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*/
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static iomux_v3_cfg_t const efikamx_uart_pads[] = {
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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MX51_PAD_UART1_RTS__UART1_RTS,
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MX51_PAD_UART1_CTS__UART1_CTS,
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};
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/*
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* SPI configuration
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*/
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static iomux_v3_cfg_t const efikamx_spi_pads[] = {
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MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
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MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
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MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
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MX51_PAD_CSPI1_SS0__GPIO4_24,
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MX51_PAD_CSPI1_SS1__GPIO4_25,
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MX51_PAD_GPIO1_6__GPIO1_6,
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};
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#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24)
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#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25)
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#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
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/*
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* PMIC configuration
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*/
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#ifdef CONFIG_MXC_SPI
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static void power_init(void)
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{
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unsigned int val;
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
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struct pmic *p;
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int ret;
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ret = pmic_init(I2C_PMIC);
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if (ret)
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return;
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p = pmic_get("FSL_PMIC");
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if (!p)
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return;
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/* Write needed to Power Gate 2 register */
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pmic_reg_read(p, REG_POWER_MISC, &val);
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val &= ~PWGT2SPIEN;
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pmic_reg_write(p, REG_POWER_MISC, val);
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/* Externally powered */
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pmic_reg_read(p, REG_CHARGE, &val);
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val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
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pmic_reg_write(p, REG_CHARGE, val);
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/* power up the system first */
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pmic_reg_write(p, REG_POWER_MISC, PWUP);
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/* Set core voltage to 1.1V */
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pmic_reg_read(p, REG_SW_0, &val);
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val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
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pmic_reg_write(p, REG_SW_0, val);
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/* Setup VCC (SW2) to 1.25 */
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pmic_reg_read(p, REG_SW_1, &val);
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val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
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pmic_reg_write(p, REG_SW_1, val);
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/* Setup 1V2_DIG1 (SW3) to 1.25 */
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pmic_reg_read(p, REG_SW_2, &val);
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val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
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pmic_reg_write(p, REG_SW_2, val);
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udelay(50);
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/* Raise the core frequency to 800MHz */
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writel(0x0, &mxc_ccm->cacrr);
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/* Set switchers in Auto in NORMAL mode & STANDBY mode */
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/* Setup the switcher mode for SW1 & SW2*/
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pmic_reg_read(p, REG_SW_4, &val);
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val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
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(SWMODE_MASK << SWMODE2_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
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pmic_reg_write(p, REG_SW_4, val);
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/* Setup the switcher mode for SW3 & SW4 */
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pmic_reg_read(p, REG_SW_5, &val);
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val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
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(SWMODE_MASK << SWMODE4_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
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pmic_reg_write(p, REG_SW_5, val);
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/* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
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pmic_reg_read(p, REG_SETTING_0, &val);
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val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
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val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
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pmic_reg_write(p, REG_SETTING_0, val);
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/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
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pmic_reg_read(p, REG_SETTING_1, &val);
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val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
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val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
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pmic_reg_write(p, REG_SETTING_1, val);
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/* Enable VGEN1, VGEN2, VDIG, VPLL */
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pmic_reg_read(p, REG_MODE_0, &val);
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val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
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pmic_reg_write(p, REG_MODE_0, val);
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/* Configure VGEN3 and VCAM regulators to use external PNP */
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val = VGEN3CONFIG | VCAMCONFIG;
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pmic_reg_write(p, REG_MODE_1, val);
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udelay(200);
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/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
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val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
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VVIDEOEN | VAUDIOEN | VSDEN;
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pmic_reg_write(p, REG_MODE_1, val);
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pmic_reg_read(p, REG_POWER_CTL2, &val);
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val |= WDIRESET;
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pmic_reg_write(p, REG_POWER_CTL2, val);
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udelay(2500);
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}
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#else
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static inline void power_init(void) { }
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#endif
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/*
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* MMC configuration
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*/
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR},
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{MMC_SDHC2_BASE_ADDR},
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};
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static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
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MX51_PAD_SD1_CMD__SD1_CMD,
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MX51_PAD_SD1_CLK__SD1_CLK,
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MX51_PAD_SD1_DATA0__SD1_DATA0,
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MX51_PAD_SD1_DATA1__SD1_DATA1,
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MX51_PAD_SD1_DATA2__SD1_DATA2,
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MX51_PAD_SD1_DATA3__SD1_DATA3,
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MX51_PAD_GPIO1_1__SD1_WP,
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};
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#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
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static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
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MX51_PAD_GPIO1_0__SD1_CD,
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MX51_PAD_EIM_CS2__SD1_CD,
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};
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#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
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#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
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static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
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MX51_PAD_SD2_CMD__SD2_CMD,
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MX51_PAD_SD2_CLK__SD2_CLK,
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MX51_PAD_SD2_DATA0__SD2_DATA0,
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MX51_PAD_SD2_DATA1__SD2_DATA1,
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MX51_PAD_SD2_DATA2__SD2_DATA2,
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MX51_PAD_SD2_DATA3__SD2_DATA3,
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MX51_PAD_GPIO1_7__SD2_WP,
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MX51_PAD_GPIO1_8__SD2_CD,
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};
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#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8)
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#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7)
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static inline uint32_t efikamx_mmc_getcd(u32 base)
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{
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if (base == MMC_SDHC1_BASE_ADDR)
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if (machine_is_efikamx())
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return EFIKAMX_SDHC1_CD;
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else
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return EFIKASB_SDHC1_CD;
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else
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return EFIKASB_SDHC2_CD;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
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int ret = !gpio_get_value(cd);
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int ret;
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/*
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* All Efika MX boards use eSDHC1 with a common write-protect GPIO
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*/
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imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
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ARRAY_SIZE(efikamx_sdhc1_pads));
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gpio_direction_input(EFIKAMX_SDHC1_WP);
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/*
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* Smartbook and Smarttop differ on the location of eSDHC1
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* carrier-detect GPIO
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*/
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if (machine_is_efikamx()) {
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imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
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gpio_direction_input(EFIKAMX_SDHC1_CD);
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} else if (machine_is_efikasb()) {
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imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
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gpio_direction_input(EFIKASB_SDHC1_CD);
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}
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
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if (machine_is_efikasb()) {
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imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
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ARRAY_SIZE(efikasb_sdhc2_pads));
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gpio_direction_input(EFIKASB_SDHC2_CD);
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gpio_direction_input(EFIKASB_SDHC2_WP);
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if (!ret)
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ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
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}
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return ret;
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}
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#endif
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/*
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* PATA
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*/
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static iomux_v3_cfg_t const efikamx_pata_pads[] = {
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MX51_PAD_NANDF_WE_B__PATA_DIOW,
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MX51_PAD_NANDF_RE_B__PATA_DIOR,
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MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
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MX51_PAD_NANDF_CLE__PATA_RESET_B,
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MX51_PAD_NANDF_WP_B__PATA_DMACK,
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MX51_PAD_NANDF_RB0__PATA_DMARQ,
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MX51_PAD_NANDF_RB1__PATA_IORDY,
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MX51_PAD_GPIO_NAND__PATA_INTRQ,
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MX51_PAD_NANDF_CS2__PATA_CS_0,
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MX51_PAD_NANDF_CS3__PATA_CS_1,
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MX51_PAD_NANDF_CS4__PATA_DA_0,
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MX51_PAD_NANDF_CS5__PATA_DA_1,
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MX51_PAD_NANDF_CS6__PATA_DA_2,
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MX51_PAD_NANDF_D15__PATA_DATA15,
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MX51_PAD_NANDF_D14__PATA_DATA14,
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MX51_PAD_NANDF_D13__PATA_DATA13,
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MX51_PAD_NANDF_D12__PATA_DATA12,
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MX51_PAD_NANDF_D11__PATA_DATA11,
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MX51_PAD_NANDF_D10__PATA_DATA10,
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MX51_PAD_NANDF_D9__PATA_DATA9,
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MX51_PAD_NANDF_D8__PATA_DATA8,
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MX51_PAD_NANDF_D7__PATA_DATA7,
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MX51_PAD_NANDF_D6__PATA_DATA6,
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MX51_PAD_NANDF_D5__PATA_DATA5,
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MX51_PAD_NANDF_D4__PATA_DATA4,
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MX51_PAD_NANDF_D3__PATA_DATA3,
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MX51_PAD_NANDF_D2__PATA_DATA2,
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MX51_PAD_NANDF_D1__PATA_DATA1,
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MX51_PAD_NANDF_D0__PATA_DATA0,
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};
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/*
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* EHCI USB
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*/
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#ifdef CONFIG_CMD_USB
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extern void setup_iomux_usb(void);
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#else
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static inline void setup_iomux_usb(void) { }
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#endif
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/*
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* LED configuration
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*
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* Smarttop LED pad config is done in the DCD
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*
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*/
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#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13)
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#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
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#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
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static iomux_v3_cfg_t const efikasb_led_pads[] = {
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MX51_PAD_GPIO1_3__GPIO1_3,
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MX51_PAD_EIM_CS0__GPIO2_25,
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};
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#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25)
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#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
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/*
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* Board initialization
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*/
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int board_early_init_f(void)
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{
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if (machine_is_efikasb()) {
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imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
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ARRAY_SIZE(efikasb_led_pads));
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gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
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gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
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} else if (machine_is_efikamx()) {
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/*
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* Set up GPIO directions for LEDs.
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* IOMUX has been done in the DCD already.
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* Turn the red LED on for pre-relocation code.
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*/
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gpio_direction_output(EFIKAMX_LED_BLUE, 0);
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gpio_direction_output(EFIKAMX_LED_GREEN, 0);
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gpio_direction_output(EFIKAMX_LED_RED, 1);
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}
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/*
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* Both these pad configurations for UART and SPI are kind of redundant
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* since they are the Power-On Defaults for the i.MX51. But, it seems we
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* should make absolutely sure that they are set up correctly.
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*/
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imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
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ARRAY_SIZE(efikamx_uart_pads));
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imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
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ARRAY_SIZE(efikamx_spi_pads));
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/* not technically required for U-Boot operation but do it anyway. */
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gpio_direction_input(EFIKAMX_PMIC_IRQ);
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/* Deselect both CS for now, otherwise NOR doesn't probe properly. */
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gpio_direction_output(EFIKAMX_SPI_SS0, 0);
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gpio_direction_output(EFIKAMX_SPI_SS1, 1);
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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int board_late_init(void)
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{
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if (machine_is_efikamx()) {
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/*
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* Set up Blue LED for "In U-Boot" status.
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* We're all relocated and ready to U-Boot!
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*/
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gpio_set_value(EFIKAMX_LED_RED, 0);
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gpio_set_value(EFIKAMX_LED_GREEN, 0);
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gpio_set_value(EFIKAMX_LED_BLUE, 1);
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}
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power_init();
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imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
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ARRAY_SIZE(efikamx_pata_pads));
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setup_iomux_usb();
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return 0;
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}
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int checkboard(void)
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{
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u32 rev = get_efikamx_rev();
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printf("Board: Genesi Efika MX ");
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if (machine_is_efikamx())
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printf("Smarttop (1.%i)\n", rev & 0xf);
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else if (machine_is_efikasb())
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printf("Smartbook\n");
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return 0;
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}
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