upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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617 lines
16 KiB
617 lines
16 KiB
/*
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* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
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* (C) Copyright 2009 Dave Srl www.dave.eu
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* (C) Copyright 2010 ifm ecomatic GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <asm/bitops.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mpc512x.h>
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#include <fdt_support.h>
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#ifdef CONFIG_MISC_INIT_R
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#include <i2c.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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static void gpio_configure(void)
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{
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immap_t *im;
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gpio512x_t *gpioregs;
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im = (immap_t *) CONFIG_SYS_IMMR;
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gpioregs = &im->gpio;
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out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
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out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
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/*
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* out_be32(&gpioregs->gpdir, 0xC2293020);
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* workaround for a hardware affect: configure direction in pieces,
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* setting all outputs at once drops the reset line too low and
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* makes us lose the MII connection (breaks ethernet for us)
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*/
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out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
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setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
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udelay(10);
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setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
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udelay(10);
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setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
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udelay(10);
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setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
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/* to turn from red to yellow when U-Boot runs */
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setbits_be32(&gpioregs->gpdat, 0x00002020);
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out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
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out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
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out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
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out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
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}
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/* the physical location of the pins */
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#define GPIOKEY_ROW_BITMASK 0x40000000
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#define GPIOKEY_ROW_UPPER 0
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#define GPIOKEY_ROW_LOWER 1
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#define GPIOKEY_COL0_BITMASK 0x20000000
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#define GPIOKEY_COL1_BITMASK 0x10000000
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#define GPIOKEY_COL2_BITMASK 0x08000000
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/* the logical presentation of pressed keys */
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#define GPIOKEY_BIT_FNLEFT (1 << 5)
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#define GPIOKEY_BIT_FNRIGHT (1 << 4)
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#define GPIOKEY_BIT_DIRUP (1 << 3)
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#define GPIOKEY_BIT_DIRLEFT (1 << 2)
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#define GPIOKEY_BIT_DIRRIGHT (1 << 1)
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#define GPIOKEY_BIT_DIRDOWN (1 << 0)
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/* the hotkey combination which starts recovery */
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#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
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GPIOKEY_BIT_DIRDOWN)
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static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
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{
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if (row)
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setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
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else
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clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
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udelay(10);
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}
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static u32 gpio_querykbd(void)
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{
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immap_t *im;
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gpio512x_t *gpioregs;
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u32 keybits;
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u32 input;
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im = (immap_t *)CONFIG_SYS_IMMR;
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gpioregs = &im->gpio;
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keybits = 0;
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/* query upper row */
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gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
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input = in_be32(&gpioregs->gpdat);
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if ((input & GPIOKEY_COL0_BITMASK) == 0)
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keybits |= GPIOKEY_BIT_FNLEFT;
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if ((input & GPIOKEY_COL1_BITMASK) == 0)
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keybits |= GPIOKEY_BIT_DIRUP;
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if ((input & GPIOKEY_COL2_BITMASK) == 0)
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keybits |= GPIOKEY_BIT_FNRIGHT;
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/* query lower row */
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gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
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input = in_be32(&gpioregs->gpdat);
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if ((input & GPIOKEY_COL0_BITMASK) == 0)
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keybits |= GPIOKEY_BIT_DIRLEFT;
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if ((input & GPIOKEY_COL1_BITMASK) == 0)
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keybits |= GPIOKEY_BIT_DIRRIGHT;
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if ((input & GPIOKEY_COL2_BITMASK) == 0)
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keybits |= GPIOKEY_BIT_DIRDOWN;
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/* return bit pattern for keys */
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return keybits;
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}
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/* excerpt from the recovery's hw_info.h */
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static int eeprom_diag = 1;
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struct __attribute__ ((__packed__)) eeprom_layout {
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char magic[3]; /** 'ifm' */
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u8 len[2]; /** content length without magic/len fields */
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u8 version[3]; /** structure version */
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u8 type; /** type of PCB */
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u8 reserved[0x37]; /** padding up to offset 0x40 */
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u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */
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};
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#define HW_COMP_MAINCPU 2
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static struct eeprom_layout eeprom_content;
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static int eeprom_was_read; /* has_been_read */
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static int eeprom_is_valid;
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static int eeprom_version;
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#define get_eeprom_field_int(name) ({ \
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int value; \
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int idx; \
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value = 0; \
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for (idx = 0; idx < sizeof(name); idx++) { \
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value <<= 8; \
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value |= name[idx]; \
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} \
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value; \
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})
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static int read_eeprom(void)
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{
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int eeprom_datalen;
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int ret;
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if (eeprom_was_read)
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return 0;
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eeprom_is_valid = 0;
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
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(uchar *)&eeprom_content, sizeof(eeprom_content));
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if (eeprom_diag) {
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printf("DIAG: %s() read rc[%d], size[%d]\n",
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__func__, ret, sizeof(eeprom_content));
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}
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if (ret != 0)
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return -1;
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eeprom_was_read = 1;
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/*
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* check validity of EEPROM content
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* (check version, length, optionally checksum)
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*/
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eeprom_is_valid = 1;
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eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
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eeprom_version = get_eeprom_field_int(eeprom_content.version);
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if (eeprom_diag) {
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printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
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__func__, eeprom_content.magic[0],
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eeprom_content.magic[1], eeprom_content.magic[2],
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eeprom_datalen, eeprom_version, eeprom_content.type);
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}
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if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
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eeprom_is_valid = 0;
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if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
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eeprom_is_valid = 0;
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if ((eeprom_version != 1) && (eeprom_version != 2))
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eeprom_is_valid = 0;
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if (eeprom_content.type != HW_COMP_MAINCPU)
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eeprom_is_valid = 0;
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if (eeprom_diag)
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printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
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return ret;
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}
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int mac_read_from_eeprom(void)
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{
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const u8 *mac;
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if (read_eeprom()) {
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printf("I2C EEPROM read failed.\n");
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return -1;
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}
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if (!eeprom_is_valid) {
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printf("I2C EEPROM content not valid\n");
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return -1;
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}
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mac = NULL;
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switch (eeprom_version) {
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case 1:
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case 2:
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mac = (const u8 *)&eeprom_content.macaddress;
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break;
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}
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if (mac && is_valid_ether_addr(mac)) {
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eth_setenv_enetaddr("ethaddr", mac);
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printf("DIAG: %s() MAC value [%s]\n",
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__func__, getenv("ethaddr"));
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}
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return 0;
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}
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/*
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* BEWARE!
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* this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
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* which the ADS, Aria or PDM360NG boards are using
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* (the steps outlined here refer to the Micron datasheet)
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*/
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u32 sdram_init_seq[] = {
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/* item 6, at least one NOP after CKE went high */
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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/* item 7, precharge all; item 8, tRP (20ns) */
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_NOP,
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/* item 9, extended mode register; item 10, tMRD 10ns) */
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CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
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CONFIG_SYS_DDRCMD_NOP,
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/*
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* item 11, (base) mode register _with_ reset DLL;
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* item 12, tMRD (10ns)
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*/
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CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
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CONFIG_SYS_MICRON_BMODE_PARAM,
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CONFIG_SYS_DDRCMD_NOP,
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/* item 13, precharge all; item 14, tRP (20ns) */
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_NOP,
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/*
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* item 15, auto refresh (i.e. refresh with CKE held high);
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* item 16, tRFC (70ns)
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*/
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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/*
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* item 17, auto refresh (i.e. refresh with CKE held high);
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* item 18, tRFC (70ns)
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*/
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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/* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
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CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
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CONFIG_SYS_DDRCMD_NOP,
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/*
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* item 21, "actually done", but make sure 200 DRAM clock cycles
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* have passed after DLL reset before READ requests are issued
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* (200 cycles at 160MHz -> 1.25 usec)
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*/
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/* EMPTY, optional, we don't do it */
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};
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phys_size_t initdram(int board_type)
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{
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return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
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}
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int misc_init_r(void)
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{
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u32 keys;
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char *s;
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int want_recovery;
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/* we use bus I2C-0 for the on-board eeprom */
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i2c_set_bus_num(0);
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/* setup GPIO directions and initial values */
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gpio_configure();
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/*
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* check the GPIO keyboard,
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* enforced start of the recovery when
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* - the appropriate keys were pressed
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* - a previous installation was aborted or has failed
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* - "some" external software told us to
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*/
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want_recovery = 0;
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keys = gpio_querykbd();
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printf("GPIO keyboard status [0x%08X]\n", keys);
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/* XXX insist in the _exact_ combination? */
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if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
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printf("GPIO keyboard requested RECOVERY\n");
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/* XXX TODO
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* refine the logic to detect the first keypress, and
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* wait to recheck IF it was the recovery combination?
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*/
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want_recovery = 1;
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}
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s = getenv("install_in_progress");
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if ((s != NULL) && (*s != '\0')) {
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printf("previous installation aborted, running RECOVERY\n");
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want_recovery = 1;
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}
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s = getenv("install_failed");
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if ((s != NULL) && (*s != '\0')) {
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printf("previous installation FAILED, running RECOVERY\n");
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want_recovery = 1;
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}
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s = getenv("want_recovery");
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if ((s != NULL) && (*s != '\0')) {
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printf("running RECOVERY according to the request\n");
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want_recovery = 1;
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}
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if (want_recovery)
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setenv("bootcmd", "run recovery");
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/*
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* boot the recovery system without waiting; boot the
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* production system without waiting by default, only
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* insert a pause (to provide a chance to get a prompt)
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* when GPIO keys were pressed during power on
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*/
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if (want_recovery)
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setenv("bootdelay", "0");
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else if (!keys)
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setenv("bootdelay", "0");
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else
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setenv("bootdelay", "2");
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/* get the ethernet MAC from I2C EEPROM */
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mac_read_from_eeprom();
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return 0;
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}
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/* setup specific IO pad configuration */
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static iopin_t ioregs_init[] = {
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{ /* LPC CS3 */
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offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
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IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
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IO_PIN_FMUX(1) | IO_PIN_DS(2),
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},
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{ /* LPC CS1 */
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offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
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IO_PIN_OVER_DRVSTR,
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IO_PIN_DS(2),
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},
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{ /* LPC CS2 */
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offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
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IO_PIN_OVER_DRVSTR,
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IO_PIN_DS(2),
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},
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{ /* LPC CS4, CS5 */
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offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
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IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
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IO_PIN_FMUX(1) | IO_PIN_DS(2),
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},
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{ /* SDHC CLK, CMD, D0, D1, D2, D3 */
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offsetof(struct ioctrl512x, io_control_pata_ior), 6,
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IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
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IO_PIN_FMUX(1) | IO_PIN_DS(2),
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},
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{ /* GPIO keyboard */
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offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
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IO_PIN_OVER_FMUX,
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IO_PIN_FMUX(3),
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},
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{ /* GPIO DN1 PF, LCD power, DN2 PF */
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offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
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IO_PIN_OVER_FMUX,
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IO_PIN_FMUX(3),
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},
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{ /* GPIO reset AS-i */
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offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
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IO_PIN_OVER_FMUX,
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IO_PIN_FMUX(3),
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},
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{ /* GPIO reset safety */
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offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
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IO_PIN_OVER_FMUX,
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IO_PIN_FMUX(3),
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},
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{ /* GPIO reset netX */
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offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
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IO_PIN_OVER_FMUX,
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IO_PIN_FMUX(3),
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},
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{ /* GPIO ma2 en */
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offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
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IO_PIN_OVER_FMUX,
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IO_PIN_FMUX(3),
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},
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{ /* GPIO SD CD, SD WP */
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offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
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IO_PIN_OVER_FMUX,
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IO_PIN_FMUX(3),
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},
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{ /* FEC RX DV */
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offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
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IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
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IO_PIN_FMUX(2) | IO_PIN_DS(2),
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},
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{ /* GPIO AS-i prog, AS-i done, LCD backlight */
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offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
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IO_PIN_OVER_FMUX,
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IO_PIN_FMUX(3),
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},
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{ /* GPIO AS-i wdg */
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offsetof(struct ioctrl512x, io_control_pci_req2), 1,
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IO_PIN_OVER_FMUX,
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IO_PIN_FMUX(3),
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},
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{ /* GPIO safety wdg */
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offsetof(struct ioctrl512x, io_control_pci_req1), 1,
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IO_PIN_OVER_FMUX,
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IO_PIN_FMUX(3),
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},
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{ /* GPIO netX wdg */
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offsetof(struct ioctrl512x, io_control_pci_req0), 1,
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IO_PIN_OVER_FMUX,
|
|
IO_PIN_FMUX(3),
|
|
},
|
|
{ /* GPIO IRQ powerfail */
|
|
offsetof(struct ioctrl512x, io_control_pci_inta), 1,
|
|
IO_PIN_OVER_FMUX,
|
|
IO_PIN_FMUX(3),
|
|
},
|
|
{ /* GPIO AS-i PWRD */
|
|
offsetof(struct ioctrl512x, io_control_pci_frame), 1,
|
|
IO_PIN_OVER_FMUX,
|
|
IO_PIN_FMUX(3),
|
|
},
|
|
{ /* GPIO LED0, LED1 */
|
|
offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
|
|
IO_PIN_OVER_FMUX,
|
|
IO_PIN_FMUX(3),
|
|
},
|
|
{ /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
|
|
offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
|
|
IO_PIN_OVER_FMUX,
|
|
IO_PIN_FMUX(3),
|
|
},
|
|
{ /* DIU clk */
|
|
offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
|
|
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_FMUX(2) | IO_PIN_DS(2),
|
|
},
|
|
{ /* FEC TX ER, CRS */
|
|
offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
|
|
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_FMUX(1) | IO_PIN_DS(2),
|
|
},
|
|
{ /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
|
|
offsetof(struct ioctrl512x, io_control_irq0), 1,
|
|
IO_PIN_OVER_FMUX,
|
|
IO_PIN_FMUX(3),
|
|
},
|
|
{ /*
|
|
* FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
|
|
* rdx 3-0, mdio, rx clk
|
|
*/
|
|
offsetof(struct ioctrl512x, io_control_psc0_0), 15,
|
|
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_FMUX(1) | IO_PIN_DS(2),
|
|
},
|
|
/* optional: make sure PSC3 remains the serial console */
|
|
{ /* LPC CS6 */
|
|
offsetof(struct ioctrl512x, io_control_psc3_4), 1,
|
|
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_FMUX(1) | IO_PIN_DS(2),
|
|
},
|
|
/* make sure PSC4 remains available for SPI,
|
|
*BUT* PSC4_1 is a GPIO kind of SS! */
|
|
{ /* enforce drive strength on the SPI pin */
|
|
offsetof(struct ioctrl512x, io_control_psc4_0), 5,
|
|
IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_DS(2),
|
|
},
|
|
{
|
|
offsetof(struct ioctrl512x, io_control_psc4_1), 1,
|
|
IO_PIN_OVER_FMUX,
|
|
IO_PIN_FMUX(3),
|
|
},
|
|
/* optional: make sure PSC5 remains available for SPI */
|
|
{ /* enforce drive strength on the SPI pin */
|
|
offsetof(struct ioctrl512x, io_control_psc5_0), 5,
|
|
IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_DS(1),
|
|
},
|
|
{ /* LPC TSIZ1 */
|
|
offsetof(struct ioctrl512x, io_control_psc6_0), 1,
|
|
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_FMUX(1) | IO_PIN_DS(2),
|
|
},
|
|
{ /* DIU hsync */
|
|
offsetof(struct ioctrl512x, io_control_psc6_1), 1,
|
|
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_FMUX(2) | IO_PIN_DS(1),
|
|
},
|
|
{ /* DIU vsync */
|
|
offsetof(struct ioctrl512x, io_control_psc6_4), 1,
|
|
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_FMUX(2) | IO_PIN_DS(1),
|
|
},
|
|
{ /* PSC7, part of DIU RGB */
|
|
offsetof(struct ioctrl512x, io_control_psc7_0), 2,
|
|
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_FMUX(2) | IO_PIN_DS(1),
|
|
},
|
|
{ /* PSC7, safety UART */
|
|
offsetof(struct ioctrl512x, io_control_psc7_2), 2,
|
|
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_FMUX(0) | IO_PIN_DS(1),
|
|
},
|
|
{ /* DIU (part of) RGB[] */
|
|
offsetof(struct ioctrl512x, io_control_psc8_3), 16,
|
|
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_FMUX(2) | IO_PIN_DS(1),
|
|
},
|
|
{ /* DIU data enable */
|
|
offsetof(struct ioctrl512x, io_control_psc11_4), 1,
|
|
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_FMUX(2) | IO_PIN_DS(1),
|
|
},
|
|
/* reduce LPB drive strength for improved EMI */
|
|
{ /* LPC OE, LPC RW */
|
|
offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
|
|
IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_DS(2),
|
|
},
|
|
{ /* LPC AX03 through LPC AD00 */
|
|
offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
|
|
IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_DS(2),
|
|
},
|
|
{ /* LPC CS5 */
|
|
offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
|
|
IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_DS(2),
|
|
},
|
|
{ /* SDHC CLK */
|
|
offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
|
|
IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_DS(2),
|
|
},
|
|
{ /* SDHC DATA */
|
|
offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
|
|
IO_PIN_OVER_DRVSTR,
|
|
IO_PIN_DS(2),
|
|
},
|
|
};
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: ifm AC14xx\n");
|
|
|
|
/* initialize function mux & slew rate IO inter alia on IO Pins */
|
|
iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
|
void ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
ft_cpu_setup(blob, bd);
|
|
}
|
|
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
|
|