upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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489 lines
14 KiB
489 lines
14 KiB
/*
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* Copyright (C) ST-Ericsson SA 2009
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <i2c.h>
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#include <asm/types.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/prcmu.h>
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#ifdef CONFIG_MMC
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#include "../../../drivers/mmc/arm_pl180_mmci.h"
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#endif
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#define NOMADIK_PER4_BASE (0x80150000)
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#define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000)
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#define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000)
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/* Power, Reset, Clock Management Unit */
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/*
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* SVA: Smart Video Accelerator
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* SIA: Smart Imaging Accelerator
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* SGA: Smart Graphic accelerator
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* B2R2: Graphic blitter
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*/
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#define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000)
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#define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004)
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#define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008)
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#define PRCM_SIAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x00C)
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#define PRCM_SAAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x010)
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#define PRCM_SGACLK_MGT_REG (PRCMU_BASE + 0x014)
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#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
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#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
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#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
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#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
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#define PRCM_SLIMCLK_MGT_REG (PRCMU_BASE + 0x028)
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#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
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#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
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#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
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#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
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#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
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#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
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#define PRCM_DMACLK_MGT_REG (PRCMU_BASE + 0x074)
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#define PRCM_B2R2CLK_MGT_REG (PRCMU_BASE + 0x078)
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#define PRCM_PLLSOC0_FREQ_REG (PRCMU_BASE + 0x080)
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#define PRCM_PLLSOC1_FREQ_REG (PRCMU_BASE + 0x084)
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#define PRCM_PLLARM_FREQ_REG (PRCMU_BASE + 0x088)
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#define PRCM_PLLDDR_FREQ_REG (PRCMU_BASE + 0x08C)
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#define PRCM_ARM_CHGCLKREQ_REG (PRCMU_BASE + 0x114)
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#define PRCM_TCR (PRCMU_BASE + 0x1C8)
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/*
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* Memory controller register
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*/
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#define DMC_BASE_ADDR 0x80156000
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#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
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int board_id; /* set in board_late_init() */
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/* PLLs for clock management registers */
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enum {
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GATED = 0,
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PLLSOC0, /* pllsw = 001, ffs() = 1 */
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PLLSOC1, /* pllsw = 010, ffs() = 2 */
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PLLDDR, /* pllsw = 100, ffs() = 3 */
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PLLARM,
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};
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static struct pll_freq_regs {
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int idx; /* index fror pll_name and pll_khz arrays */
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uint32_t addr;
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} pll_freq_regs[] = {
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{PLLSOC0, PRCM_PLLSOC0_FREQ_REG},
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{PLLSOC1, PRCM_PLLSOC1_FREQ_REG},
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{PLLDDR, PRCM_PLLDDR_FREQ_REG},
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{PLLARM, PRCM_PLLARM_FREQ_REG},
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{0, 0},
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};
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static const char *pll_name[5] = {"GATED", "SOC0", "SOC1", "DDR", "ARM"};
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static uint32_t pll_khz[5]; /* use ffs(pllsw(reg)) as index for 0..3 */
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static struct clk_mgt_regs {
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uint32_t addr;
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uint32_t val;
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const char *descr;
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} clk_mgt_regs[] = {
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/* register content taken from bootrom settings */
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{PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */
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{PRCM_ACLK_MGT_REG, 0x0125, "ACLK"}, /* ena, SOC0/5, 160 MHz */
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{PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */
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{PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */
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{PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */
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{PRCM_SGACLK_MGT_REG, 0x0024, "SGA"}, /* dis, SOC0/4, 200 MHz */
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{PRCM_UARTCLK_MGT_REG, 0x0300, "UART"}, /* ena, GATED, CLK38 */
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{PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"}, /* dis, GATED, CLK38 */
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{PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"}, /* ena, SOC0/16, 50 MHz */
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{PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */
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{PRCM_PER1CLK_MGT_REG, 0x126, "PER1"}, /* ena, SOC0/6, 133 MHz */
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{PRCM_PER2CLK_MGT_REG, 0x126, "PER2"}, /* ena, SOC0/6, 133 MHz */
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{PRCM_PER3CLK_MGT_REG, 0x126, "PER3"}, /* ena, SOC0/6, 133 MHz */
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{PRCM_PER5CLK_MGT_REG, 0x126, "PER5"}, /* ena, SOC0/6, 133 MHz */
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{PRCM_PER6CLK_MGT_REG, 0x126, "PER6"}, /* ena, SOC0/6, 133 MHz */
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{PRCM_PER7CLK_MGT_REG, 0x128, "PER7"}, /* ena, SOC0/8, 100 MHz */
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{PRCM_DMACLK_MGT_REG, 0x125, "DMA"}, /* ena, SOC0/5, 160 MHz */
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{PRCM_B2R2CLK_MGT_REG, 0x025, "B2R2"}, /* dis, SOC0/5, 160 MHz */
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{0, 0, NULL},
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};
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static void init_regs(void);
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SHOW_BOOT_PROGRESS)
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void show_boot_progress(int progress)
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{
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printf("Boot reached stage %d\n", progress);
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}
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#endif
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_early_init_f(void)
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{
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init_regs();
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return 0;
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}
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int board_init(void)
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{
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uint32_t unused_cols_rows;
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unsigned int nrows;
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unsigned int ncols;
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gd->bd->bi_arch_number = 0x1A4;
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gd->bd->bi_boot_params = 0x00000100;
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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/*
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* Assumption: 2 CS active, both CS have same layout.
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* 15 rows max, 11 cols max (controller spec).
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* memory chip has 8 banks, I/O width 32 bit.
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* The correct way would be to read MR#8: I/O width and density,
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* but this requires locking against the PRCMU firmware.
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* Simplified approach:
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* Read number of unused rows and columns from mem controller.
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* size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes
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*/
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unused_cols_rows = readl(DMC_CTL_97);
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nrows = 15 - (unused_cols_rows & 0x07);
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ncols = 11 - ((unused_cols_rows & 0x0700) >> 8);
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gd->bd->bi_dram[0].size = 2 * (1 << (nrows + ncols)) * 8 * 4;
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icache_enable();
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE_1;
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return 0;
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}
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unsigned int addr_vall_arr[] = {
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0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO: Enable reqd only */
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0x8011F008, 0x00001CFF, /* Clocks for HSI TODO: Enable reqd only */
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0x8000F000, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
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0x8000F008, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
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0x80157020, 0x00000150, /* I2C 48MHz clock */
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0x8012F000, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
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0x8012F008, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
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0xA03DF000, 0x0000000D, /* Clock for MTU Timers */
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0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */
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0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
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0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
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0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */
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0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */
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0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */
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0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */
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0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */
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0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */
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0x801571E4, 0x0000000C, /* PRCMU settings for B2R2,
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PRCM_APE_RESETN_SET_REG */
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0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */
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0xA03FF000, 0x00000003, /* USB */
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0xA03FF008, 0x00000001, /* USB */
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0xA03FE00C, 0x00000000, /* USB */
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0xA03FE020, 0x00000FFF, /* USB */
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0xA03FE024, 0x00000000 /* USB */
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};
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#ifdef CONFIG_BOARD_LATE_INIT
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/*
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* called after all initialisation were done, but before the generic
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* mmc_initialize().
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*/
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int board_late_init(void)
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{
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uchar byte;
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/*
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* Determine and set board_id environment variable
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* 0: mop500, 1: href500
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* Above boards have different GPIO expander chips which we can
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* distinguish by the chip id.
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*
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* The board_id environment variable is needed for the Linux bootargs.
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*/
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(void) i2c_set_bus_num(0);
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(void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1);
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if (byte == 0x01) {
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board_id = 0;
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setenv("board_id", "0");
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} else {
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board_id = 1;
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setenv("board_id", "1");
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}
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#ifdef CONFIG_MMC
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u8500_mmc_power_init();
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/*
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* config extended GPIO pins for level shifter and
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* SDMMC_ENABLE
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*/
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if (board_id == 0) {
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/* MOP500 */
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byte = 0x0c;
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(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x89, 1, &byte, 1);
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(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x83, 1, &byte, 1);
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} else {
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/* HREF */
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/* set the direction of GPIO KPY9 and KPY10 */
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byte = 0x06;
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(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC8, 1, &byte, 1);
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/* must be a multibyte access */
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(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC4, 1,
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(uchar []) {0x06, 0x06}, 2);
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}
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#endif /* CONFIG_MMC */
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/*
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* Create a memargs variable which points uses either the memargs256 or
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* memargs512 environment variable, depending on the memory size.
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* memargs is used to build the bootargs, memargs256 and memargs512 are
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* stored in the environment.
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*/
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if (gd->bd->bi_dram[0].size == 0x10000000) {
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setenv("memargs", "setenv bootargs ${bootargs} ${memargs256}");
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setenv("mem", "256M");
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} else {
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setenv("memargs", "setenv bootargs ${bootargs} ${memargs512}");
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setenv("mem", "512M");
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}
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return 0;
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}
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#endif /* CONFIG_BOARD_LATE_INIT */
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static void early_gpio_setup(struct gpio_register *gpio_reg, u32 bits)
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{
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writel(readl(&gpio_reg->gpio_dats) | bits, &gpio_reg->gpio_dats);
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writel(readl(&gpio_reg->gpio_pdis) & ~bits, &gpio_reg->gpio_pdis);
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}
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static void init_regs(void)
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{
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/* FIXME Remove magic register array settings for ED also */
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struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE;
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/* Enable timers */
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writel(1 << 17, &prcmu->tcr);
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u8500_prcmu_enable(&prcmu->per1clk_mgt);
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u8500_prcmu_enable(&prcmu->per2clk_mgt);
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u8500_prcmu_enable(&prcmu->per3clk_mgt);
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u8500_prcmu_enable(&prcmu->per5clk_mgt);
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u8500_prcmu_enable(&prcmu->per6clk_mgt);
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u8500_prcmu_enable(&prcmu->per7clk_mgt);
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u8500_prcmu_enable(&prcmu->uartclk_mgt);
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u8500_prcmu_enable(&prcmu->i2cclk_mgt);
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u8500_prcmu_enable(&prcmu->sdmmcclk_mgt);
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u8500_clock_enable(1, 9, -1); /* GPIO0 */
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u8500_clock_enable(2, 11, -1); /* GPIO1 */
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u8500_clock_enable(3, 8, -1); /* GPIO2 */
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u8500_clock_enable(5, 1, -1); /* GPIO3 */
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u8500_clock_enable(3, 6, 6); /* UART2 */
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gpio_altfuncenable(GPIO_ALT_I2C_0, "I2C0");
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u8500_clock_enable(3, 3, 3); /* I2C0 */
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early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x60000000);
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gpio_altfuncenable(GPIO_ALT_UART_2, "UART2");
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early_gpio_setup((struct gpio_register *)U8500_GPIO_6_BASE, 0x0000ffe0);
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gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC");
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early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x0000ffe0);
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gpio_altfuncenable(GPIO_ALT_SD_CARD0, "SDCARD");
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u8500_clock_enable(1, 5, 5); /* SDI0 */
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u8500_clock_enable(2, 4, 2); /* SDI4 */
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u8500_clock_enable(6, 7, -1); /* MTU0 */
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u8500_clock_enable(3, 4, 4); /* SDI2 */
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early_gpio_setup((struct gpio_register *)U8500_GPIO_4_BASE, 0x000007ff);
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gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC");
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/*
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* Enabling clocks for all devices which are AMBA devices in the
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* kernel. Otherwise they will not get probe()'d because the
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* peripheral ID register will not be powered.
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*/
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/* XXX: some of these differ between ED/V1 */
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u8500_clock_enable(1, 1, 1); /* UART1 */
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u8500_clock_enable(1, 0, 0); /* UART0 */
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u8500_clock_enable(3, 2, 2); /* SSP1 */
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u8500_clock_enable(3, 1, 1); /* SSP0 */
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u8500_clock_enable(2, 8, -1); /* SPI0 */
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u8500_clock_enable(2, 5, 3); /* MSP2 */
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}
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#ifdef CONFIG_MMC
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static int u8500_mmci_board_init(void)
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{
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enum gpio_error error;
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struct gpio_register *gpio_base_address;
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gpio_base_address = (void *)(U8500_GPIO_0_BASE);
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gpio_base_address->gpio_dats |= 0xFFC0000;
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gpio_base_address->gpio_pdis &= ~0xFFC0000;
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/* save the GPIO0 AFSELA register */
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error = gpio_altfuncenable(GPIO_ALT_SD_CARD0, "MMC");
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if (error != GPIO_OK) {
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printf("u8500_mmci_board_init() gpio_altfuncenable failed\n");
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return -ENODEV;
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}
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return 0;
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}
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int board_mmc_init(bd_t *bd)
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{
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struct pl180_mmc_host *host;
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if (u8500_mmci_board_init())
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return -ENODEV;
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host = malloc(sizeof(struct pl180_mmc_host));
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if (!host)
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return -ENOMEM;
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memset(host, 0, sizeof(*host));
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strcpy(host->name, "MMC");
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host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
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host->pwr_init = INIT_PWR;
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host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
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host->voltages = VOLTAGE_WINDOW_MMC;
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host->caps = 0;
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host->clock_in = ARM_MCLK;
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host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
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host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
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return arm_pl180_mmci_init(host);
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}
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#endif
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/*
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* get_pll_freq_khz - return PLL frequency in kHz
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*/
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static uint32_t get_pll_freq_khz(uint32_t inclk_khz, uint32_t freq_reg)
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{
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uint32_t idf, ldf, odf, seldiv, phi;
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|
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/*
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* PLLOUTCLK = PHI = (INCLK*LDF)/(2*ODF*IDF) if SELDIV2=0
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* PLLOUTCLK = PHI = (INCLK*LDF)/(4*ODF*IDF) if SELDIV2=1
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* where:
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* IDF=R(2:0) (when R=000, IDF=1d)
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* LDF = 2*D(7:0) (D must be greater than or equal to 6)
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* ODF = N(5:0) (when N=000000, 0DF=1d)
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*/
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idf = (freq_reg & 0x70000) >> 16;
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ldf = (freq_reg & 0xff) * 2;
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odf = (freq_reg & 0x3f00) >> 8;
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seldiv = (freq_reg & 0x01000000) >> 24;
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phi = (inclk_khz * ldf) / (2 * odf * idf);
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if (seldiv)
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phi = phi/2;
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return phi;
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}
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int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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uint32_t inclk_khz;
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uint32_t reg, phi;
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uint32_t clk_khz;
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unsigned int clk_sel;
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struct clk_mgt_regs *clks = clk_mgt_regs;
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struct pll_freq_regs *plls = pll_freq_regs;
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|
|
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/*
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* Go through list of PLLs.
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* Initialise pll out frequency array (pll_khz) and print frequency.
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*/
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inclk_khz = 38400; /* 38.4 MHz */
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while (plls->addr) {
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reg = readl(plls->addr);
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phi = get_pll_freq_khz(inclk_khz, reg);
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pll_khz[plls->idx] = phi;
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printf("%s PLL out frequency: %d.%d Mhz\n",
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pll_name[plls->idx], phi/1000, phi % 1000);
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plls++;
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}
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|
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/* check ARM clock source */
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reg = readl(PRCM_ARM_CHGCLKREQ_REG);
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printf("A9 running on %s\n",
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(reg & 1) ? "external clock" : "ARM PLL");
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|
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/* go through list of clk_mgt_reg */
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printf("\n%19s %9s %7s %9s enabled\n",
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"name(addr)", "value", "PLL", "CLK[MHz]");
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while (clks->addr) {
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reg = readl(clks->addr);
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|
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/* convert bit position into array index */
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clk_sel = ffs((reg >> 5) & 0x7); /* PLLSW[2:0] */
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|
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if (reg & 0x200)
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clk_khz = 38400; /* CLK38 is set */
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else if ((reg & 0x1f) == 0)
|
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/* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */
|
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clk_khz = 0;
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else
|
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clk_khz = pll_khz[clk_sel] / (reg & 0x1f);
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|
|
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printf("%9s(%08x): %08x, %6s, %4d.%03d, %s\n",
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clks->descr, clks->addr, reg, pll_name[clk_sel],
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clk_khz / 1000, clk_khz % 1000,
|
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(reg & 0x100) ? "ena" : "dis");
|
|
clks++;
|
|
}
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|
|
|
return 0;
|
|
}
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|
|
|
U_BOOT_CMD(
|
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clkinfo, 1, 1, do_clkinfo,
|
|
"print clock info",
|
|
""
|
|
);
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|