upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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216 lines
7.3 KiB
216 lines
7.3 KiB
/*
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* Copyright (C) 2004 PaulReynolds@lhsolutions.com
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*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#include <ppc4xx_enet.h>
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#include <netdev.h>
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#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
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void show_reset_reg(void);
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int lcd_init(void);
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int board_early_init_f (void)
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{
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unsigned long reg;
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volatile unsigned int *GpioOdr;
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volatile unsigned int *GpioTcr;
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volatile unsigned int *GpioOr;
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/*-------------------------------------------------------------------------+
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| Initialize EBC CONFIG
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+-------------------------------------------------------------------------*/
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mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
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EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
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EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
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EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
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/*-------------------------------------------------------------------------+
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| 64MB FLASH. Initialize bank 0 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
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EBC_BXAP_BCE_DISABLE |
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EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
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EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
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EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
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EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
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EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
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/*-------------------------------------------------------------------------+
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| FPGA. Initialize bank 1 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
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EBC_BXAP_BCE_DISABLE |
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EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
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EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
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EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
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EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
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/*-------------------------------------------------------------------------+
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| LCM. Initialize bank 2 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
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EBC_BXAP_BCE_DISABLE |
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EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
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EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
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EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
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EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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/*-------------------------------------------------------------------------+
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| TMP. Initialize bank 3 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
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EBC_BXAP_BCE_DISABLE |
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EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
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EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
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EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
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EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
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EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
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/*-------------------------------------------------------------------------+
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| Connector 4~7. Initialize bank 3~ 7 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(PB4AP,0);
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mtebc(PB4CR,0);
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mtebc(PB5AP,0);
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mtebc(PB5CR,0);
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mtebc(PB6AP,0);
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mtebc(PB6CR,0);
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mtebc(PB7AP,0);
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mtebc(PB7CR,0);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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/*
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* Because of the interrupt handling rework to handle 440GX interrupts
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* with the common code, we needed to change names of the UIC registers.
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* Here the new relationship:
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*
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* U-Boot name 440GX name
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* -----------------------
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* UIC0 UICB0
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* UIC1 UIC0
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* UIC2 UIC1
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* UIC3 UIC2
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*/
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mtdcr (UIC1SR, 0xffffffff); /* clear all */
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mtdcr (UIC1ER, 0x00000000); /* disable all */
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mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
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mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
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mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
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mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (UIC1SR, 0xffffffff); /* clear all */
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mtdcr (UIC2SR, 0xffffffff); /* clear all */
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mtdcr (UIC2ER, 0x00000000); /* disable all */
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mtdcr (UIC2CR, 0x00000000); /* all non-critical */
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mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
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mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
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mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (UIC2SR, 0xffffffff); /* clear all */
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mtdcr (UIC3SR, 0xffffffff); /* clear all */
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mtdcr (UIC3ER, 0x00000000); /* disable all */
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mtdcr (UIC3CR, 0x00000000); /* all non-critical */
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mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
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mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
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mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (UIC3SR, 0xffffffff); /* clear all */
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mtdcr (UIC0SR, 0xfc000000); /* clear all */
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mtdcr (UIC0ER, 0x00000000); /* disable all */
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mtdcr (UIC0CR, 0x00000000); /* all non-critical */
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mtdcr (UIC0PR, 0xfc000000); /* */
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mtdcr (UIC0TR, 0x00000000); /* */
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mtdcr (UIC0VR, 0x00000001); /* */
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/* Enable two GPIO 10~11 and TraceA signal */
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mfsdr(SDR0_PFC0,reg);
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reg |= 0x00300000;
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mtsdr(SDR0_PFC0,reg);
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mfsdr(SDR0_PFC1,reg);
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reg |= 0x00100000;
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mtsdr(SDR0_PFC1,reg);
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/* Set GPIO 10 and 11 as output */
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GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
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GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704);
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GpioOr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700);
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*GpioOdr &= ~(0x00300000);
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*GpioTcr |= 0x00300000;
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*GpioOr |= 0x00300000;
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return 0;
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}
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int misc_init_r(void)
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{
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lcd_init();
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return 0;
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}
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
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if (s != NULL) {
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puts (", serial# ");
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puts (s);
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}
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putc ('\n');
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#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
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show_reset_reg();
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#endif
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return (0);
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}
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis);
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return pci_eth_init(bis);
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}
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