upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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153 lines
3.0 KiB
153 lines
3.0 KiB
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008,2009
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct pci_controller x86_hose;
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int pci_early_init_hose(struct pci_controller **hosep)
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{
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struct pci_controller *hose;
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hose = calloc(1, sizeof(struct pci_controller));
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if (!hose)
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return -ENOMEM;
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board_pci_setup_hose(hose);
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pci_setup_type1(hose);
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hose->last_busno = pci_hose_scan(hose);
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gd->hose = hose;
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*hosep = hose;
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return 0;
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}
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__weak int board_pci_pre_scan(struct pci_controller *hose)
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{
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return 0;
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}
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__weak int board_pci_post_scan(struct pci_controller *hose)
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{
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return 0;
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}
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void pci_init_board(void)
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{
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struct pci_controller *hose = &x86_hose;
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/* Stop using the early hose */
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gd->hose = NULL;
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board_pci_setup_hose(hose);
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pci_setup_type1(hose);
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pci_register_hose(hose);
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board_pci_pre_scan(hose);
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hose->last_busno = pci_hose_scan(hose);
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board_pci_post_scan(hose);
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}
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static struct pci_controller *get_hose(void)
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{
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if (gd->hose)
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return gd->hose;
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return pci_bus_to_hose(0);
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}
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unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
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{
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uint8_t value;
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pci_hose_read_config_byte(get_hose(), dev, where, &value);
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return value;
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}
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unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
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{
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uint16_t value;
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pci_hose_read_config_word(get_hose(), dev, where, &value);
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return value;
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}
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unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
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{
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uint32_t value;
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pci_hose_read_config_dword(get_hose(), dev, where, &value);
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return value;
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}
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void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
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{
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pci_hose_write_config_byte(get_hose(), dev, where, value);
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}
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void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
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{
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pci_hose_write_config_word(get_hose(), dev, where, value);
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}
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void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
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{
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pci_hose_write_config_dword(get_hose(), dev, where, value);
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}
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int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
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ulong *valuep, enum pci_size_t size)
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{
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outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
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switch (size) {
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case PCI_SIZE_8:
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*valuep = inb(PCI_REG_DATA + (offset & 3));
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break;
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case PCI_SIZE_16:
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*valuep = inw(PCI_REG_DATA + (offset & 2));
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break;
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case PCI_SIZE_32:
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*valuep = inl(PCI_REG_DATA);
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break;
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}
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return 0;
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}
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int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
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ulong value, enum pci_size_t size)
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{
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outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
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switch (size) {
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case PCI_SIZE_8:
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outb(value, PCI_REG_DATA + (offset & 3));
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break;
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case PCI_SIZE_16:
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outw(value, PCI_REG_DATA + (offset & 2));
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break;
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case PCI_SIZE_32:
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outl(value, PCI_REG_DATA);
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break;
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}
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return 0;
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}
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