upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
69 lines
2.4 KiB
69 lines
2.4 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright (C) 2013 Boundary Devices
|
|
*/
|
|
/* ZQ Calibration */
|
|
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
|
|
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
|
|
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
|
|
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
|
|
/*
|
|
* DQS gating, read delay, write delay calibration values
|
|
* based on calibration compare of 0x00ffff00
|
|
*/
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200
|
|
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202
|
|
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172
|
|
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C
|
|
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49
|
|
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133
|
|
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E
|
|
/* read data bit delay */
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
|
|
/* Complete calibration by forced measurment */
|
|
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
|
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
|
/* in DDR3, 64-bit mode, only MMDC0 is initiated */
|
|
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
|
|
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
|
|
DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
|
|
DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63
|
|
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
|
|
DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
|
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
|
|
DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21
|
|
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
|
|
DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
|
|
/* MR2 */
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a
|
|
/* MR3 */
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
|
|
/* MR1 */
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
|
|
/* MR0 */
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038
|
|
/* ZQ calibration */
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
|
|
/* final ddr setup */
|
|
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
|
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
|
|
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007
|
|
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
|
|
DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
|
|