upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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299 lines
7.9 KiB
299 lines
7.9 KiB
/*
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* Copyright (C) 2012 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/at91sam9x5_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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#include <lcd.h>
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#include <atmel_hlcdc.h>
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#ifdef CONFIG_MACB
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#include <net.h>
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#endif
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#include <netdev.h>
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#ifdef CONFIG_LCD_INFO
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#include <nand.h>
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#include <version.h>
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#endif
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#ifdef CONFIG_ATMEL_SPI
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#include <spi.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_CMD_NAND
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static void at91sam9x5ek_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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unsigned long csa;
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/* Enable CS3 */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
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/* NAND flash on D16 */
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csa |= AT91_MATRIX_NFD0_ON_D16;
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/* Configure IO drive */
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csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
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AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(1),
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&smc->cs[3].mode);
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writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
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at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
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at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
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at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
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at91_set_a_periph(AT91_PIO_PORTD, 6, 1);
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at91_set_a_periph(AT91_PIO_PORTD, 7, 1);
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at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
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at91_set_a_periph(AT91_PIO_PORTD, 9, 1);
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at91_set_a_periph(AT91_PIO_PORTD, 10, 1);
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at91_set_a_periph(AT91_PIO_PORTD, 11, 1);
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at91_set_a_periph(AT91_PIO_PORTD, 12, 1);
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at91_set_a_periph(AT91_PIO_PORTD, 13, 1);
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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if (has_emac0())
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rc = macb_eth_initialize(0,
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(void *)ATMEL_BASE_EMAC0, 0x00);
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if (has_emac1())
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rc = macb_eth_initialize(1,
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(void *)ATMEL_BASE_EMAC1, 0x00);
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#endif
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return rc;
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}
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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.vl_col = 800,
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.vl_row = 480,
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.vl_clk = 24000000,
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.vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL,
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.vl_bpix = LCD_BPP,
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.vl_tft = 1,
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.vl_clk_pol = 1,
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.vl_hsync_len = 128,
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.vl_left_margin = 64,
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.vl_right_margin = 64,
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.vl_vsync_len = 2,
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.vl_upper_margin = 22,
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.vl_lower_margin = 21,
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.mmio = ATMEL_BASE_LCDC,
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};
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void lcd_enable(void)
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{
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if (has_lcdc())
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at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */
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}
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void lcd_disable(void)
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{
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if (has_lcdc())
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at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */
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}
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static void at91sam9x5ek_lcd_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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if (has_lcdc()) {
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at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */
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at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */
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at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */
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at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */
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at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
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at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */
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at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
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at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
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at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
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at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
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at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
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at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
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at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
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at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
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at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
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at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
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at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
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at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
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at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
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at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
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at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
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at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
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at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
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at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
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at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
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at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
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at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
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at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
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at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
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at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
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writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
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}
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}
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#ifdef CONFIG_LCD_INFO
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void lcd_show_board_info(void)
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{
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ulong dram_size, nand_size;
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int i;
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char temp[32];
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if (has_lcdc()) {
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lcd_printf("%s\n", U_BOOT_VERSION);
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lcd_printf("(C) 2012 ATMEL Corp\n");
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lcd_printf("at91support@atmel.com\n");
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lcd_printf("%s CPU at %s MHz\n",
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get_cpu_name(),
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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dram_size += gd->bd->bi_dram[i].size;
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nand_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_size += nand_info[i].size;
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lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
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dram_size >> 20,
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nand_size >> 20);
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}
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}
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#endif /* CONFIG_LCD_INFO */
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#endif /* CONFIG_LCD */
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/* SPI chip select control */
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#ifdef CONFIG_ATMEL_SPI
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs < 2;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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switch (slave->cs) {
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case 1:
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at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
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break;
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case 0:
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default:
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at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
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break;
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}
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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switch (slave->cs) {
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case 1:
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at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
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break;
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case 0:
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default:
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at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
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break;
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}
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}
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#endif /* CONFIG_ATMEL_SPI */
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int board_early_init_f(void)
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{
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at91_seriald_hw_init();
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return 0;
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}
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int board_init(void)
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{
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/* arch number of AT91SAM9X5EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_CMD_NAND
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at91sam9x5ek_nand_hw_init();
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#endif
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#ifdef CONFIG_ATMEL_SPI
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at91_spi0_hw_init(1 << 0);
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at91_spi0_hw_init(1 << 4);
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#endif
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#ifdef CONFIG_MACB
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at91_macb_hw_init();
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#endif
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#ifdef CONFIG_LCD
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at91sam9x5ek_lcd_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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