upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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606 lines
14 KiB
606 lines
14 KiB
/*
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* Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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* Copyright (C) 2011 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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#include <asm/processor.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/* WDT */
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write32 WDTCSR_A, WDTCSR_D
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/* MMU */
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write32 MMUCR_A, MMUCR_D
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write32 FRQCR2_A, FRQCR2_D
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write32 FRQCR0_A, FRQCR0_D
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write32 CS0CTRL_A, CS0CTRL_D
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write32 CS1CTRL_A, CS1CTRL_D
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write32 CS0CTRL2_A, CS0CTRL2_D
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write32 CSPWCR0_A, CSPWCR0_D
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write32 CSPWCR1_A, CSPWCR1_D
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write32 CS1GDST_A, CS1GDST_D
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# clock mode check
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mov.l MODEMR, r1
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mov.l @r1, r0
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and #6, r0 /* Check 1 and 2 bit.*/
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cmp/eq #2, r0 /* 0x02 is 533Mhz mode */
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bt init_lbsc_533
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init_lbsc_400:
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write32 CSWCR0_A, CSWCR0_D_400
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write32 CSWCR1_A, CSWCR1_D
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bra init_dbsc3_400_pad
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nop
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.align 2
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MODEMR: .long 0xFFCC0020
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WDTCSR_A: .long 0xFFCC0004
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WDTCSR_D: .long 0xA5000000
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MMUCR_A: .long 0xFF000010
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MMUCR_D: .long 0x00000004
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FRQCR2_A: .long 0xFFC80008
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FRQCR2_D: .long 0x00000000
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FRQCR0_A: .long 0xFFC80000
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FRQCR0_D: .long 0xCF000001
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CS0CTRL_A: .long 0xFF800200
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CS0CTRL_D: .long 0x00000020
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CS1CTRL_A: .long 0xFF800204
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CS1CTRL_D: .long 0x00000020
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CS0CTRL2_A: .long 0xFF800220
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CS0CTRL2_D: .long 0x00004000
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CSPWCR0_A: .long 0xFF800280
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CSPWCR0_D: .long 0x00000000
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CSPWCR1_A: .long 0xFF800284
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CSPWCR1_D: .long 0x00000000
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CS1GDST_A: .long 0xFF8002C0
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CS1GDST_D: .long 0x00000011
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init_lbsc_533:
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write32 CSWCR0_A, CSWCR0_D_533
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write32 CSWCR1_A, CSWCR1_D
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bra init_dbsc3_533_pad
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nop
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.align 2
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CSWCR0_A: .long 0xFF800230
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CSWCR0_D_533: .long 0x01120104
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CSWCR0_D_400: .long 0x02120114
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/* CSWCR0_D_400: .long 0x01160116 */
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CSWCR1_A: .long 0xFF800234
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CSWCR1_D: .long 0x077F077F
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/* CSWCR1_D_400: .long 0x00120012 */
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init_dbsc3_400_pad:
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write32 DBPDCNT3_A, DBPDCNT3_D
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wait_timer WAIT_200US_400
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write32 DBPDCNT0_A, DBPDCNT0_D_400
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write32 DBPDCNT3_A, DBPDCNT3_D0
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write32 DBPDCNT1_A, DBPDCNT1_D
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write32 DBPDCNT3_A, DBPDCNT3_D1
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wait_timer WAIT_32MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D2
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wait_timer WAIT_100US_400
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write32 DBPDCNT3_A, DBPDCNT3_D3
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wait_timer WAIT_16MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D4
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wait_timer WAIT_200US_400
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write32 DBPDCNT3_A, DBPDCNT3_D5
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wait_timer WAIT_1MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D6
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wait_timer WAIT_10KMCLK
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bra init_dbsc3_ctrl_400
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nop
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.align 2
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init_dbsc3_533_pad:
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write32 DBPDCNT3_A, DBPDCNT3_D
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wait_timer WAIT_200US_533
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write32 DBPDCNT0_A, DBPDCNT0_D_533
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write32 DBPDCNT3_A, DBPDCNT3_D0
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write32 DBPDCNT1_A, DBPDCNT1_D
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write32 DBPDCNT3_A, DBPDCNT3_D1
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wait_timer WAIT_32MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D2
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wait_timer WAIT_100US_533
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write32 DBPDCNT3_A, DBPDCNT3_D3
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wait_timer WAIT_16MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D4
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wait_timer WAIT_200US_533
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write32 DBPDCNT3_A, DBPDCNT3_D5
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wait_timer WAIT_1MCLK
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write32 DBPDCNT3_A, DBPDCNT3_D6
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wait_timer WAIT_10KMCLK
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bra init_dbsc3_ctrl_533
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nop
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.align 2
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WAIT_200US_400: .long 40000
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WAIT_200US_533: .long 53300
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WAIT_100US_400: .long 20000
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WAIT_100US_533: .long 26650
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WAIT_32MCLK: .long 32
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WAIT_16MCLK: .long 16
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WAIT_1MCLK: .long 1
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WAIT_10KMCLK: .long 10000
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DBPDCNT0_A: .long 0xFE800200
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DBPDCNT0_D_533: .long 0x00010245
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DBPDCNT0_D_400: .long 0x00010235
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DBPDCNT1_A: .long 0xFE800204
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DBPDCNT1_D: .long 0x00000014
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DBPDCNT3_A: .long 0xFE80020C
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DBPDCNT3_D: .long 0x80000000
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DBPDCNT3_D0: .long 0x800F0000
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DBPDCNT3_D1: .long 0x800F1000
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DBPDCNT3_D2: .long 0x820F1000
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DBPDCNT3_D3: .long 0x860F1000
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DBPDCNT3_D4: .long 0x870F1000
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DBPDCNT3_D5: .long 0x870F3000
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DBPDCNT3_D6: .long 0x870F7000
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init_dbsc3_ctrl_400:
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write32 DBKIND_A, DBKIND_D
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write32 DBCONF_A, DBCONF_D
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write32 DBTR0_A, DBTR0_D_400
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write32 DBTR1_A, DBTR1_D_400
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write32 DBTR2_A, DBTR2_D
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write32 DBTR3_A, DBTR3_D_400
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write32 DBTR4_A, DBTR4_D_400
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write32 DBTR5_A, DBTR5_D_400
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write32 DBTR6_A, DBTR6_D_400
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write32 DBTR7_A, DBTR7_D
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write32 DBTR8_A, DBTR8_D_400
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write32 DBTR9_A, DBTR9_D
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write32 DBTR10_A, DBTR10_D_400
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write32 DBTR11_A, DBTR11_D
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write32 DBTR12_A, DBTR12_D_400
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write32 DBTR13_A, DBTR13_D_400
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write32 DBTR14_A, DBTR14_D
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write32 DBTR15_A, DBTR15_D
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write32 DBTR16_A, DBTR16_D_400
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write32 DBTR17_A, DBTR17_D_400
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write32 DBTR18_A, DBTR18_D_400
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write32 DBBL_A, DBBL_D
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write32 DBRNK0_A, DBRNK0_D
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write32 DBCMD_A, DBCMD_D0_400
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write32 DBCMD_A, DBCMD_D1
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write32 DBCMD_A, DBCMD_D2
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write32 DBCMD_A, DBCMD_D3
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write32 DBCMD_A, DBCMD_D4
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write32 DBCMD_A, DBCMD_D5_400
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write32 DBCMD_A, DBCMD_D6
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write32 DBCMD_A, DBCMD_D7
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write32 DBCMD_A, DBCMD_D8
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write32 DBCMD_A, DBCMD_D9_400
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write32 DBCMD_A, DBCMD_D10
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write32 DBCMD_A, DBCMD_D11
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write32 DBCMD_A, DBCMD_D12
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write32 DBBS0CNT1_A, DBBS0CNT1_D
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write32 DBPDNCNF_A, DBPDNCNF_D
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write32 DBRFCNF0_A, DBRFCNF0_D
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write32 DBRFCNF1_A, DBRFCNF1_D_400
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write32 DBRFCNF2_A, DBRFCNF2_D
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write32 DBRFEN_A, DBRFEN_D
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write32 DBACEN_A, DBACEN_D
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write32 DBACEN_A, DBACEN_D
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/* Dummy read */
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mov.l DBWAIT_A, r1
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synco
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mov.l @r1, r0
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synco
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/* Dummy read */
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mov.l SDRAM_A, r1
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synco
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mov.l @r1, r0
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synco
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/* need sleep 186A0 */
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bra init_pfc_sh7734
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nop
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.align 2
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init_dbsc3_ctrl_533:
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write32 DBKIND_A, DBKIND_D
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write32 DBCONF_A, DBCONF_D
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write32 DBTR0_A, DBTR0_D_533
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write32 DBTR1_A, DBTR1_D_533
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write32 DBTR2_A, DBTR2_D
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write32 DBTR3_A, DBTR3_D_533
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write32 DBTR4_A, DBTR4_D_533
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write32 DBTR5_A, DBTR5_D_533
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write32 DBTR6_A, DBTR6_D_533
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write32 DBTR7_A, DBTR7_D
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write32 DBTR8_A, DBTR8_D_533
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write32 DBTR9_A, DBTR9_D
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write32 DBTR10_A, DBTR10_D_533
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write32 DBTR11_A, DBTR11_D
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write32 DBTR12_A, DBTR12_D_533
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write32 DBTR13_A, DBTR13_D_533
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write32 DBTR14_A, DBTR14_D
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write32 DBTR15_A, DBTR15_D
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write32 DBTR16_A, DBTR16_D_533
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write32 DBTR17_A, DBTR17_D_533
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write32 DBTR18_A, DBTR18_D_533
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write32 DBBL_A, DBBL_D
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write32 DBRNK0_A, DBRNK0_D
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write32 DBCMD_A, DBCMD_D0_533
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write32 DBCMD_A, DBCMD_D1
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write32 DBCMD_A, DBCMD_D2
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write32 DBCMD_A, DBCMD_D3
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write32 DBCMD_A, DBCMD_D4
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write32 DBCMD_A, DBCMD_D5_533
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write32 DBCMD_A, DBCMD_D6
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write32 DBCMD_A, DBCMD_D7
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write32 DBCMD_A, DBCMD_D8
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write32 DBCMD_A, DBCMD_D9_533
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write32 DBCMD_A, DBCMD_D10
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write32 DBCMD_A, DBCMD_D11
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write32 DBCMD_A, DBCMD_D12
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write32 DBBS0CNT1_A, DBBS0CNT1_D
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write32 DBPDNCNF_A, DBPDNCNF_D
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write32 DBRFCNF0_A, DBRFCNF0_D
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write32 DBRFCNF1_A, DBRFCNF1_D_533
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write32 DBRFCNF2_A, DBRFCNF2_D
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write32 DBRFEN_A, DBRFEN_D
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write32 DBACEN_A, DBACEN_D
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write32 DBACEN_A, DBACEN_D
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/* Dummy read */
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mov.l DBWAIT_A, r1
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synco
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mov.l @r1, r0
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synco
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/* Dummy read */
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mov.l SDRAM_A, r1
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synco
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mov.l @r1, r0
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synco
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/* need sleep 186A0 */
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bra init_pfc_sh7734
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nop
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.align 2
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DBKIND_A: .long 0xFE800020
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DBKIND_D: .long 0x00000005
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DBCONF_A: .long 0xFE800024
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DBCONF_D: .long 0x0D030A01
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DBTR0_A: .long 0xFE800040
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DBTR0_D_533:.long 0x00000004
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DBTR0_D_400:.long 0x00000003
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DBTR1_A: .long 0xFE800044
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DBTR1_D_533:.long 0x00000003
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DBTR1_D_400:.long 0x00000002
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DBTR2_A: .long 0xFE800048
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DBTR2_D: .long 0x00000000
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DBTR3_A: .long 0xFE800050
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DBTR3_D_533:.long 0x00000004
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DBTR3_D_400:.long 0x00000003
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DBTR4_A: .long 0xFE800054
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DBTR4_D_533:.long 0x00050004
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DBTR4_D_400:.long 0x00050003
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DBTR5_A: .long 0xFE800058
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DBTR5_D_533:.long 0x0000000F
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DBTR5_D_400:.long 0x0000000B
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DBTR6_A: .long 0xFE80005C
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DBTR6_D_533:.long 0x0000000B
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DBTR6_D_400:.long 0x00000008
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DBTR7_A: .long 0xFE800060
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DBTR7_D: .long 0x00000002 /* common value */
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DBTR8_A: .long 0xFE800064
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DBTR8_D_533:.long 0x0000000D
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DBTR8_D_400:.long 0x0000000A
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DBTR9_A: .long 0xFE800068
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DBTR9_D: .long 0x00000002 /* common value */
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DBTR10_A: .long 0xFE80006C
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DBTR10_D_533:.long 0x00000004
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DBTR10_D_400:.long 0x00000003
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DBTR11_A: .long 0xFE800070
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DBTR11_D: .long 0x00000008 /* common value */
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DBTR12_A: .long 0xFE800074
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DBTR12_D_533:.long 0x00000009
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DBTR12_D_400:.long 0x00000008
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DBTR13_A: .long 0xFE800078
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DBTR13_D_533:.long 0x00000022
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DBTR13_D_400:.long 0x0000001A
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DBTR14_A: .long 0xFE80007C
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DBTR14_D: .long 0x00070002 /* common value */
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DBTR15_A: .long 0xFE800080
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DBTR15_D: .long 0x00000003 /* common value */
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DBTR16_A: .long 0xFE800084
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DBTR16_D_533:.long 0x120A1001
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DBTR16_D_400:.long 0x12091001
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DBTR17_A: .long 0xFE800088
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DBTR17_D_533:.long 0x00040000
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DBTR17_D_400:.long 0x00030000
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DBTR18_A: .long 0xFE80008C
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DBTR18_D_533:.long 0x02010200
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DBTR18_D_400:.long 0x02000207
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DBBL_A: .long 0xFE8000B0
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DBBL_D: .long 0x00000000
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DBRNK0_A: .long 0xFE800100
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DBRNK0_D: .long 0x00000001
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DBCMD_A: .long 0xFE800018
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DBCMD_D0_533: .long 0x1100006B
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DBCMD_D0_400: .long 0x11000050
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DBCMD_D1: .long 0x0B000000 /* common value */
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DBCMD_D2: .long 0x2A004000 /* common value */
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DBCMD_D3: .long 0x2B006000 /* common value */
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DBCMD_D4: .long 0x29002004 /* common value */
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DBCMD_D5_533: .long 0x28000743
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DBCMD_D5_400: .long 0x28000533
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DBCMD_D6: .long 0x0B000000 /* common value */
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DBCMD_D7: .long 0x0C000000 /* common value */
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DBCMD_D8: .long 0x0C000000 /* common value */
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DBCMD_D9_533: .long 0x28000643
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DBCMD_D9_400: .long 0x28000433
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DBCMD_D10: .long 0x000000C8 /* common value */
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DBCMD_D11: .long 0x29002384 /* common value */
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DBCMD_D12: .long 0x29002004 /* common value */
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DBBS0CNT1_A: .long 0xFE800304
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DBBS0CNT1_D: .long 0x00000000
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DBPDNCNF_A: .long 0xFE800180
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DBPDNCNF_D: .long 0x00000200
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DBRFCNF0_A: .long 0xFE8000E0
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DBRFCNF0_D: .long 0x000001FF
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DBRFCNF1_A: .long 0xFE8000E4
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DBRFCNF1_D_533: .long 0x00000805
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DBRFCNF1_D_400: .long 0x00000618
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DBRFCNF2_A: .long 0xFE8000E8
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DBRFCNF2_D: .long 0x00000000
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DBRFEN_A: .long 0xFE800014
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DBRFEN_D: .long 0x00000001
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DBACEN_A: .long 0xFE800010
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DBACEN_D: .long 0x00000001
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DBWAIT_A: .long 0xFE80001C
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SDRAM_A: .long 0x0C000000
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init_pfc_sh7734:
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write32 PFC_PMMR_A, PFC_PMMR_MODESEL1
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write32 PFC_MODESEL1_A, PFC_MODESEL1_D
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write32 PFC_PMMR_A, PFC_PMMR_MODESEL2
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write32 PFC_MODESEL2_A, PFC_MODESEL2_D
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write32 PFC_PMMR_A, PFC_PMMR_IPSR3
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write32 PFC_IPSR3_A, PFC_IPSR3_D
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write32 PFC_PMMR_A, PFC_PMMR_IPSR4
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write32 PFC_IPSR4_A, PFC_IPSR4_D
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write32 PFC_PMMR_A, PFC_PMMR_IPSR11
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write32 PFC_IPSR11_A, PFC_IPSR11_D
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write32 PFC_PMMR_A, PFC_PMMR_GPSR0
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write32 PFC_GPSR0_A, PFC_GPSR0_D
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write32 PFC_PMMR_A, PFC_PMMR_GPSR1
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write32 PFC_GPSR1_A, PFC_GPSR1_D
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write32 PFC_PMMR_A, PFC_PMMR_GPSR2
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write32 PFC_GPSR2_A, PFC_GPSR2_D
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write32 PFC_PMMR_A, PFC_PMMR_GPSR3
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write32 PFC_GPSR3_A, PFC_GPSR3_D
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write32 PFC_PMMR_A, PFC_PMMR_GPSR4
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write32 PFC_GPSR4_A, PFC_GPSR4_D
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write32 PFC_PMMR_A, PFC_PMMR_GPSR5
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write32 PFC_GPSR5_A, PFC_GPSR5_D
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/* sleep 186A0 */
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write32 GPIO2_INOUTSEL1_A, GPIO2_INOUTSEL1_D
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write32 GPIO1_OUTDT1_A, GPIO1_OUTDT1_D
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write32 GPIO2_INOUTSEL2_A, GPIO2_INOUTSEL2_D
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write32 GPIO2_OUTDT2_A, GPIO2_OUTDT2_D
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write32 GPIO4_INOUTSEL4_A, GPIO4_INOUTSEL4_D
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write32 GPIO4_OUTDT4_A, GPIO4_OUTDT4_D
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write32 CCR_A, CCR_D
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stc sr, r0
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mov.l SR_MASK_D, r1
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and r1, r0
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ldc r0, sr
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rts
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nop
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.align 2
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PFC_PMMR_A: .long 0xFFFC0000
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/* MODESEL
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* 28: Select IEBUS Group B
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*/
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PFC_MODESEL1_A: .long 0xFFFC004C
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PFC_MODESEL1_D: .long 0x10000000
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PFC_PMMR_MODESEL1: .long 0xEFFFFFFF
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/* MODESEL
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* 9: Select SCIF3 Group B
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* 7: Select SCIF2 Group B
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* 4: Select SCIF1 Group B
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*/
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PFC_MODESEL2_A: .long 0xFFFC0050
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PFC_MODESEL2_D: .long 0x00000290
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PFC_PMMR_MODESEL2: .long 0xFFFFFD6F
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# Enable functios
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# SD1_DAT2_A SD1_DAT1_A, SD1_DAT0_A,
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# EXWAIT0, RDW/RW, SD1_CMD_A, SD1_WP_A,
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# SD1_CD_A, TX3_B, RX3_B, CS1, D15
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PFC_IPSR3_A: .long 0xFFFC0028
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PFC_IPSR3_D: .long 0x09209248
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PFC_PMMR_IPSR3: .long 0xF6DF6DB7
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|
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# Enable functios
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# RMII0_MDIO_A , RMII0_MDC_A,
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# RMII0_CRS_DV_A, RMII0_RX_ER_A,
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# RMII0_TXD_EN_A, MII0_RXD1_A
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PFC_IPSR4_A: .long 0xFFFC002C
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PFC_IPSR4_D: .long 0x0001B6DB
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PFC_PMMR_IPSR4: .long 0xFFFE4924
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|
|
|
# Enable functios
|
|
# DACK1, DREQ1, SD1_DAT3_A, SD1_CLK_A, IERX_B,
|
|
# IETX_B, TX0_A, RMII0_TXD0_A,
|
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# RMII0_TXD1_A, RMII0_TXD0_A, SDSEL, SDA0, SDA1, SCL1
|
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PFC_IPSR11_A: .long 0xFFFC0048
|
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PFC_IPSR11_D: .long 0x002C89B0
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PFC_PMMR_IPSR11:.long 0xFFD3764F
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|
|
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PFC_GPSR0_A: .long 0xFFFC0004
|
|
PFC_GPSR0_D: .long 0xFFFFFFFF
|
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PFC_PMMR_GPSR0: .long 0x00000000
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|
|
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PFC_GPSR1_A: .long 0xFFFC0008
|
|
PFC_GPSR1_D: .long 0x7FBF7FFF
|
|
PFC_PMMR_GPSR1: .long 0x80408000
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|
|
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PFC_GPSR2_A: .long 0xFFFC000C
|
|
PFC_GPSR2_D: .long 0xBFC07EDF
|
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PFC_PMMR_GPSR2: .long 0x403F8120
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|
|
|
PFC_GPSR3_A: .long 0xFFFC0010
|
|
PFC_GPSR3_D: .long 0xFFFFFFFF
|
|
PFC_PMMR_GPSR3: .long 0x00000000
|
|
|
|
PFC_GPSR4_A: .long 0xFFFC0014
|
|
#if 0 /* orig */
|
|
PFC_GPSR4_D: .long 0xFFFFFFFF
|
|
PFC_PMMR_GPSR4: .long 0x00000000
|
|
#else
|
|
PFC_GPSR4_D: .long 0xFBFFFFFF
|
|
PFC_PMMR_GPSR4: .long 0x04000000
|
|
#endif
|
|
|
|
PFC_GPSR5_A: .long 0xFFFC0018
|
|
PFC_GPSR5_D: .long 0x00000C01
|
|
PFC_PMMR_GPSR5: .long 0xFFFFF3FE
|
|
|
|
I2C_ICCR2_A: .long 0xFFC70001
|
|
I2C_ICCR2_D: .long 0x00
|
|
I2C_ICCR2_D1: .long 0x20
|
|
|
|
GPIO2_INOUTSEL1_A: .long 0xFFC41004
|
|
GPIO2_INOUTSEL1_D: .long 0x80408000
|
|
GPIO1_OUTDT1_A: .long 0xFFC41008 /* bit15: LED4, bit22: LED5 */
|
|
GPIO1_OUTDT1_D: .long 0x80408000
|
|
GPIO2_INOUTSEL2_A: .long 0xFFC42004
|
|
GPIO2_INOUTSEL2_D: .long 0x40000120
|
|
GPIO2_OUTDT2_A: .long 0xFFC42008
|
|
GPIO2_OUTDT2_D: .long 0x40000120
|
|
GPIO4_INOUTSEL4_A: .long 0xFFC44004
|
|
GPIO4_INOUTSEL4_D: .long 0x04000000
|
|
GPIO4_OUTDT4_A: .long 0xFFC44008
|
|
GPIO4_OUTDT4_D: .long 0x04000000
|
|
|
|
CCR_A: .long 0xFF00001C
|
|
CCR_D: .long 0x0000090B
|
|
SR_MASK_D: .long 0xEFFFFF0F
|
|
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