upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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97 lines
3.0 KiB
97 lines
3.0 KiB
/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2014-2016, Toradex AG
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/*
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* DDR3 settings
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* MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
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* memory bus width: 64 bits x16/x32/x64
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* MX6DL ddr is limited to 800 MHz(400 MHz clock)
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* memory bus width: 64 bits x16/x32/x64
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* MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
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* memory bus width: 32 bits x16/x32
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*/
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DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
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DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
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DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
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/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
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DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
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DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
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DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
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DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
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DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
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DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
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DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
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DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
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DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
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DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
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DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
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/* (differential input) */
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DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
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/* (differential input) */
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DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
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/* disable ddr pullups */
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DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
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/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
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DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
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/* Read data DQ Byte0-3 delay */
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
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/*
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* MDMISC mirroring interleaved (row/bank/col)
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*/
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
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/*
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* MDSCR con_req
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*/
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
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