upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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251 lines
8.1 KiB
251 lines
8.1 KiB
/*
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* (C) Copyright 2005-2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2003
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* Martijn de Gouw, Prodrive B.V., martijn.de.gouw@prodrive.nl
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*
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* Configuation settings for the IXDPG425 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
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#define CONFIG_IXDPG425 1 /* on an IXDPG425 Board */
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#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
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#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
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/*
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* Ethernet
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*/
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#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_PHY_ADDR 5 /* NPE0 PHY address */
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#define CONFIG_HAS_ETH1
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#define CONFIG_PHY1_ADDR 4 /* NPE1 PHY address */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
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/*
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* Misc configuration options
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*/
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */
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#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
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#define CFG_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (256 << 10)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
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#define CFG_LOAD_ADDR 0x00010000 /* default load address */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/***************************************************************
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* Platform/Board specific defines start here.
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***************************************************************/
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/*-----------------------------------------------------------------------
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* Default configuration (environment varibles...)
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*----------------------------------------------------------------------*/
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"hostname=ixdpg425\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/eldk/arm\0" \
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"bootfile=/tftpboot/ixdpg425/uImage\0" \
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"kernel_addr=50080000\0" \
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"ramdisk_addr=50200000\0" \
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"load=tftp 100000 /tftpboot/ixdpg425/u-boot.bin\0" \
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"update=protect off 50000000 5003ffff;era 50000000 5003ffff;" \
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"cp.b 100000 50000000 40000;" \
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"setenv filesize;saveenv\0" \
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"upd=run load update\0" \
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""
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#define CONFIG_BOOTCOMMAND "run net_nfs"
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */
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#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
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#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
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#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
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#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
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#define CFG_DRAM_BASE 0x00000000
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#define CFG_DRAM_SIZE 0x01000000
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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/*
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* Expansion bus settings
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*/
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#define CFG_EXP_CS0 0xbcd23c42
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/*
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* SDRAM settings
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*/
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#define CFG_SDR_CONFIG 0x18
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#define CFG_SDR_MODE_CONFIG 0x1
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#define CFG_SDRAM_REFRESH_CNT 0x81a
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/*
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* FLASH and environment organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
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#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
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#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*
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* GPIO settings
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*/
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#define CFG_GPIO_PCI_INTA_N 6
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#define CFG_GPIO_PCI_INTB_N 7
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#define CFG_GPIO_SWITCH_RESET_N 8
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#define CFG_GPIO_SLIC_RESET_N 13
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#define CFG_GPIO_PCI_CLK 14
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#define CFG_GPIO_EXTBUS_CLK 15
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/*
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32
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#endif /* __CONFIG_H */
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