upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/include/dt-bindings/clock/r8a7793-cpg-mssr.h

48 lines
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/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7793 CPG Core Clocks */
#define R8A7793_CLK_Z 0
#define R8A7793_CLK_ZG 1
#define R8A7793_CLK_ZTR 2
#define R8A7793_CLK_ZTRD2 3
#define R8A7793_CLK_ZT 4
#define R8A7793_CLK_ZX 5
#define R8A7793_CLK_ZS 6
#define R8A7793_CLK_HP 7
#define R8A7793_CLK_I 8
#define R8A7793_CLK_B 9
#define R8A7793_CLK_LB 10
#define R8A7793_CLK_P 11
#define R8A7793_CLK_CL 12
#define R8A7793_CLK_M2 13
#define R8A7793_CLK_ADSP 14
#define R8A7793_CLK_ZB3 15
#define R8A7793_CLK_ZB3D2 16
#define R8A7793_CLK_DDR 17
#define R8A7793_CLK_SDH 18
#define R8A7793_CLK_SD0 19
#define R8A7793_CLK_SD2 20
#define R8A7793_CLK_SD3 21
#define R8A7793_CLK_MMC0 22
#define R8A7793_CLK_MP 23
#define R8A7793_CLK_SSP 24
#define R8A7793_CLK_SSPRS 25
#define R8A7793_CLK_QSPI 26
#define R8A7793_CLK_CP 27
#define R8A7793_CLK_RCAN 28
#define R8A7793_CLK_R 29
#define R8A7793_CLK_OSC 30
#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */