upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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101 lines
2.7 KiB
101 lines
2.7 KiB
/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/pantheon.h>
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#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
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#define SET_MRVL_ID (1<<8)
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#define L2C_RAM_SEL (1<<4)
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int arch_cpu_init(void)
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{
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u32 val;
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struct panthcpu_registers *cpuregs =
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(struct panthcpu_registers*) PANTHEON_CPU_BASE;
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struct panthapb_registers *apbclkres =
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(struct panthapb_registers*) PANTHEON_APBC_BASE;
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struct panthmpmu_registers *mpmu =
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(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
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struct panthapmu_registers *apmu =
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(struct panthapmu_registers *) PANTHEON_APMU_BASE;
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/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
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val = readl(&cpuregs->cpu_conf);
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val = val | SET_MRVL_ID;
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writel(val, &cpuregs->cpu_conf);
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/* Turn on clock gating (PMUM_CCGR) */
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writel(0xFFFFFFFF, &mpmu->ccgr);
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/* Turn on clock gating (PMUM_ACGR) */
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writel(0xFFFFFFFF, &mpmu->acgr);
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/* Turn on uart2 clock */
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writel(UARTCLK14745KHZ, &apbclkres->uart0);
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/* Enable GPIO clock */
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writel(APBC_APBCLK, &apbclkres->gpio);
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#ifdef CONFIG_I2C_MV
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/* Enable I2C clock */
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writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
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writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
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#endif
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#ifdef CONFIG_MV_SDHCI
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/* Enable mmc clock */
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writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
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&apmu->sd1);
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writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
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&apmu->sd3);
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#endif
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icache_enable();
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return 0;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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u32 id;
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struct panthcpu_registers *cpuregs =
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(struct panthcpu_registers*) PANTHEON_CPU_BASE;
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id = readl(&cpuregs->chip_id);
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printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
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return 0;
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}
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#endif
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#ifdef CONFIG_I2C_MV
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void i2c_clk_enable(void)
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{
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}
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#endif
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