upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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608 lines
18 KiB
608 lines
18 KiB
/**
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* @file IxNpeMhConfig.c
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*
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* @author Intel Corporation
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* @date 18 Jan 2002
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*
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* @brief This file contains the implementation of the private API for the
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* Configuration module.
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/*
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* Put the system defined include files required.
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*/
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/*
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* Put the user defined include files required.
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*/
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#include "IxOsal.h"
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#include "IxNpeMhMacros_p.h"
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#include "IxNpeMhConfig_p.h"
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/*
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* #defines and macros used in this file.
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*/
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#define IX_NPE_MH_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
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* retries before
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* timeout
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*/
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/*
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* Typedefs whose scope is limited to this file.
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*/
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/**
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* @struct IxNpeMhConfigStats
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*
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* @brief This structure is used to maintain statistics for the
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* Configuration module.
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*/
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typedef struct
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{
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UINT32 outFifoReads; /**< outFifo reads */
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UINT32 inFifoWrites; /**< inFifo writes */
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UINT32 maxInFifoFullRetries; /**< max retries if inFIFO full */
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UINT32 maxOutFifoEmptyRetries; /**< max retries if outFIFO empty */
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} IxNpeMhConfigStats;
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/*
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* Variable declarations global to this file only. Externs are followed by
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* static variables.
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*/
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IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] =
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{
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{
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0,
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IX_NPEMH_NPEA_INT,
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0,
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0,
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0,
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0,
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0,
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NULL,
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FALSE
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},
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{
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0,
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IX_NPEMH_NPEB_INT,
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0,
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0,
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0,
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0,
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0,
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NULL,
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FALSE
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},
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{
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0,
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IX_NPEMH_NPEC_INT,
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0,
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0,
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0,
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0,
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0,
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NULL,
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FALSE
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}
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};
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PRIVATE IxNpeMhConfigStats ixNpeMhConfigStats[IX_NPEMH_NUM_NPES];
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/*
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* Extern function prototypes.
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*/
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/*
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* Static function prototypes.
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*/
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PRIVATE
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void ixNpeMhConfigIsr (void *parameter);
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/*
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* Function definition: ixNpeMhConfigIsr
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*/
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PRIVATE
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void ixNpeMhConfigIsr (void *parameter)
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{
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IxNpeMhNpeId npeId = (IxNpeMhNpeId)parameter;
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UINT32 ofint;
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volatile UINT32 *statusReg =
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(UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister;
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
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"ixNpeMhConfigIsr\n");
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/* get the OFINT (OutFifo interrupt) bit of the status register */
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IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofint, IX_NPEMH_NPE_STAT_OFINT);
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/* if the OFINT status bit is set */
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if (ofint)
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{
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/* if there is an ISR registered for this NPE */
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if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
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{
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/* invoke the ISR routine */
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ixNpeMhConfigNpeInfo[npeId].isr (npeId);
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}
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else
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{
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/* if we don't service the interrupt the NPE will continue */
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/* to trigger the interrupt indefinitely */
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IX_NPEMH_ERROR_REPORT ("No ISR registered to service "
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"interrupt\n");
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}
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}
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
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"ixNpeMhConfigIsr\n");
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}
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/*
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* Function definition: ixNpeMhConfigInitialize
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*/
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void ixNpeMhConfigInitialize (
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IxNpeMhNpeInterrupts npeInterrupts)
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{
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IxNpeMhNpeId npeId;
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UINT32 virtualAddr[IX_NPEMH_NUM_NPES];
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
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"ixNpeMhConfigInitialize\n");
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/* Request a mapping for the NPE-A config register address space */
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virtualAddr[IX_NPEMH_NPEID_NPEA] =
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(UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEA_BASE,
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IX_OSAL_IXP400_NPEA_MAP_SIZE);
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IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEA]);
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/* Request a mapping for the NPE-B config register address space */
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virtualAddr[IX_NPEMH_NPEID_NPEB] =
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(UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEB_BASE,
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IX_OSAL_IXP400_NPEB_MAP_SIZE);
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IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEB]);
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/* Request a mapping for the NPE-C config register address space */
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virtualAddr[IX_NPEMH_NPEID_NPEC] =
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(UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEC_BASE,
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IX_OSAL_IXP400_NPEC_MAP_SIZE);
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IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEC]);
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/* for each NPE ... */
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for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
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{
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/* declare a convenience pointer */
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IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
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/* store the virtual addresses of the NPE registers for later use */
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npeInfo->virtualRegisterBase = virtualAddr[npeId];
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npeInfo->statusRegister = virtualAddr[npeId] + IX_NPEMH_NPESTAT_OFFSET;
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npeInfo->controlRegister = virtualAddr[npeId] + IX_NPEMH_NPECTL_OFFSET;
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npeInfo->inFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
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npeInfo->outFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET;
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/* for test purposes - to verify the register addresses */
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IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d status register = "
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"0x%08X\n", npeId, npeInfo->statusRegister);
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IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d control register = "
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"0x%08X\n", npeId, npeInfo->controlRegister);
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IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d inFifo register = "
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"0x%08X\n", npeId, npeInfo->inFifoRegister);
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IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d outFifo register = "
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"0x%08X\n", npeId, npeInfo->outFifoRegister);
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/* connect our ISR to the NPE interrupt */
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(void) ixOsalIrqBind (
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npeInfo->interruptId, ixNpeMhConfigIsr, (void *)npeId);
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/* initialise a mutex for this NPE */
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(void) ixOsalMutexInit (&npeInfo->mutex);
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/* if we should service the NPE's "outFIFO not empty" interrupt */
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if (npeInterrupts == IX_NPEMH_NPEINTERRUPTS_YES)
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{
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/* enable the NPE's "outFIFO not empty" interrupt */
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ixNpeMhConfigNpeInterruptEnable (npeId);
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}
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else
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{
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/* disable the NPE's "outFIFO not empty" interrupt */
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ixNpeMhConfigNpeInterruptDisable (npeId);
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}
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}
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
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"ixNpeMhConfigInitialize\n");
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}
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/*
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* Function definition: ixNpeMhConfigUninit
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*/
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void ixNpeMhConfigUninit (void)
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{
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IxNpeMhNpeId npeId;
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
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"ixNpeMhConfigUninit\n");
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/* for each NPE ... */
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for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++)
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{
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/* declare a convenience pointer */
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IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId];
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/* disconnect ISR */
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ixOsalIrqUnbind(npeInfo->interruptId);
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/* destroy mutex associated with this NPE */
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ixOsalMutexDestroy(&npeInfo->mutex);
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IX_OSAL_MEM_UNMAP (npeInfo->virtualRegisterBase);
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npeInfo->virtualRegisterBase = 0;
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npeInfo->statusRegister = 0;
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npeInfo->controlRegister = 0;
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npeInfo->inFifoRegister = 0;
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npeInfo->outFifoRegister = 0;
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}
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
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"ixNpeMhConfigUninit\n");
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}
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/*
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* Function definition: ixNpeMhConfigIsrRegister
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*/
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void ixNpeMhConfigIsrRegister (
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IxNpeMhNpeId npeId,
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IxNpeMhConfigIsr isr)
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{
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
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"ixNpeMhConfigIsrRegister\n");
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/* check if there is already an ISR registered for this NPE */
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if (ixNpeMhConfigNpeInfo[npeId].isr != NULL)
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{
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IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, "Over-writing registered NPE ISR\n");
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}
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/* save the ISR routine with the NPE info */
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ixNpeMhConfigNpeInfo[npeId].isr = isr;
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
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"ixNpeMhConfigIsrRegister\n");
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}
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/*
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* Function definition: ixNpeMhConfigNpeInterruptEnable
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*/
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BOOL ixNpeMhConfigNpeInterruptEnable (
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IxNpeMhNpeId npeId)
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{
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UINT32 ofe;
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volatile UINT32 *controlReg =
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(UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
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/* get the OFE (OutFifoEnable) bit of the control register */
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IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
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/* if the interrupt is disabled then we must enable it */
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if (!ofe)
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{
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/* set the OFE (OutFifoEnable) bit of the control register */
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/* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
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/* time for the write to have effect */
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IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
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(IX_NPEMH_NPE_CTL_OFE |
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IX_NPEMH_NPE_CTL_OFEWE),
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(IX_NPEMH_NPE_CTL_OFE |
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IX_NPEMH_NPE_CTL_OFEWE));
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}
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/* return the previous state of the interrupt */
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return (ofe != 0);
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}
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/*
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* Function definition: ixNpeMhConfigNpeInterruptDisable
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*/
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BOOL ixNpeMhConfigNpeInterruptDisable (
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IxNpeMhNpeId npeId)
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{
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UINT32 ofe;
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volatile UINT32 *controlReg =
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(UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister;
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/* get the OFE (OutFifoEnable) bit of the control register */
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IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE);
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/* if the interrupt is enabled then we must disable it */
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if (ofe)
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{
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/* unset the OFE (OutFifoEnable) bit of the control register */
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/* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */
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/* time for the write to have effect */
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IX_NPEMH_REGISTER_WRITE_BITS (controlReg,
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(0 |
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IX_NPEMH_NPE_CTL_OFEWE),
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(IX_NPEMH_NPE_CTL_OFE |
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IX_NPEMH_NPE_CTL_OFEWE));
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}
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/* return the previous state of the interrupt */
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return (ofe != 0);
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}
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/*
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* Function definition: ixNpeMhConfigMessageIdGet
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*/
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IxNpeMhMessageId ixNpeMhConfigMessageIdGet (
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IxNpeMhMessage message)
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{
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/* return the most-significant byte of the first word of the */
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/* message */
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return ((IxNpeMhMessageId) ((message.data[0] >> 24) & 0xFF));
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}
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/*
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* Function definition: ixNpeMhConfigNpeIdIsValid
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*/
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BOOL ixNpeMhConfigNpeIdIsValid (
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IxNpeMhNpeId npeId)
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{
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/* check that the npeId parameter is within the range of valid IDs */
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return (npeId >= 0 && npeId < IX_NPEMH_NUM_NPES);
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}
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/*
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* Function definition: ixNpeMhConfigLockGet
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*/
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void ixNpeMhConfigLockGet (
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IxNpeMhNpeId npeId)
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{
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
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"ixNpeMhConfigLockGet\n");
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/* lock the mutex for this NPE */
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(void) ixOsalMutexLock (&ixNpeMhConfigNpeInfo[npeId].mutex,
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IX_OSAL_WAIT_FOREVER);
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/* disable the NPE's "outFIFO not empty" interrupt */
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ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
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ixNpeMhConfigNpeInterruptDisable (npeId);
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
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"ixNpeMhConfigLockGet\n");
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}
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/*
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* Function definition: ixNpeMhConfigLockRelease
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*/
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void ixNpeMhConfigLockRelease (
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IxNpeMhNpeId npeId)
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{
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering "
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"ixNpeMhConfigLockRelease\n");
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/* if the interrupt was previously enabled */
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if (ixNpeMhConfigNpeInfo[npeId].oldInterruptState)
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{
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/* enable the NPE's "outFIFO not empty" interrupt */
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ixNpeMhConfigNpeInfo[npeId].oldInterruptState =
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ixNpeMhConfigNpeInterruptEnable (npeId);
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}
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/* unlock the mutex for this NPE */
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(void) ixOsalMutexUnlock (&ixNpeMhConfigNpeInfo[npeId].mutex);
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IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
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"ixNpeMhConfigLockRelease\n");
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}
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/*
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* Function definition: ixNpeMhConfigInFifoWrite
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*/
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IX_STATUS ixNpeMhConfigInFifoWrite (
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IxNpeMhNpeId npeId,
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IxNpeMhMessage message)
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{
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volatile UINT32 *npeInFifo =
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(UINT32 *)ixNpeMhConfigNpeInfo[npeId].inFifoRegister;
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UINT32 retriesCount = 0;
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/* write the first word of the message to the NPE's inFIFO */
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IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[0]);
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/* need to wait for room to write second word - see SCR #493,
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poll for maximum number of retries, if exceed maximum
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retries, exit from while loop */
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while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
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&& ixNpeMhConfigInFifoIsFull (npeId))
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{
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retriesCount++;
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}
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/* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
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if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
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{
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return IX_NPEMH_CRITICAL_NPE_ERR;
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}
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/* write the second word of the message to the NPE's inFIFO */
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IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[1]);
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/* record in the stats the maximum number of retries needed */
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if (ixNpeMhConfigStats[npeId].maxInFifoFullRetries < retriesCount)
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{
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ixNpeMhConfigStats[npeId].maxInFifoFullRetries = retriesCount;
|
|
}
|
|
|
|
/* update statistical info */
|
|
ixNpeMhConfigStats[npeId].inFifoWrites++;
|
|
|
|
return IX_SUCCESS;
|
|
}
|
|
|
|
/*
|
|
* Function definition: ixNpeMhConfigOutFifoRead
|
|
*/
|
|
|
|
IX_STATUS ixNpeMhConfigOutFifoRead (
|
|
IxNpeMhNpeId npeId,
|
|
IxNpeMhMessage *message)
|
|
{
|
|
volatile UINT32 *npeOutFifo =
|
|
(UINT32 *)ixNpeMhConfigNpeInfo[npeId].outFifoRegister;
|
|
UINT32 retriesCount = 0;
|
|
|
|
/* read the first word of the message from the NPE's outFIFO */
|
|
IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[0]);
|
|
|
|
/* need to wait for NPE to write second word - see SCR #493
|
|
poll for maximum number of retries, if exceed maximum
|
|
retries, exit from while loop */
|
|
while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount)
|
|
&& ixNpeMhConfigOutFifoIsEmpty (npeId))
|
|
{
|
|
retriesCount++;
|
|
}
|
|
|
|
/* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */
|
|
if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount)
|
|
{
|
|
return IX_NPEMH_CRITICAL_NPE_ERR;
|
|
}
|
|
|
|
/* read the second word of the message from the NPE's outFIFO */
|
|
IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[1]);
|
|
|
|
/* record in the stats the maximum number of retries needed */
|
|
if (ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries < retriesCount)
|
|
{
|
|
ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = retriesCount;
|
|
}
|
|
|
|
/* update statistical info */
|
|
ixNpeMhConfigStats[npeId].outFifoReads++;
|
|
|
|
return IX_SUCCESS;
|
|
}
|
|
|
|
/*
|
|
* Function definition: ixNpeMhConfigShow
|
|
*/
|
|
|
|
void ixNpeMhConfigShow (
|
|
IxNpeMhNpeId npeId)
|
|
{
|
|
/* show the message fifo read counter */
|
|
IX_NPEMH_SHOW ("Message FIFO reads",
|
|
ixNpeMhConfigStats[npeId].outFifoReads);
|
|
|
|
/* show the message fifo write counter */
|
|
IX_NPEMH_SHOW ("Message FIFO writes",
|
|
ixNpeMhConfigStats[npeId].inFifoWrites);
|
|
|
|
/* show the max retries performed when inFIFO full */
|
|
IX_NPEMH_SHOW ("Max inFIFO Full retries",
|
|
ixNpeMhConfigStats[npeId].maxInFifoFullRetries);
|
|
|
|
/* show the max retries performed when outFIFO empty */
|
|
IX_NPEMH_SHOW ("Max outFIFO Empty retries",
|
|
ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries);
|
|
|
|
/* show the current status of the inFifo */
|
|
ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
|
|
"InFifo is %s and %s\n",
|
|
(ixNpeMhConfigInFifoIsEmpty (npeId) ?
|
|
(int) "EMPTY" : (int) "NOT EMPTY"),
|
|
(ixNpeMhConfigInFifoIsFull (npeId) ?
|
|
(int) "FULL" : (int) "NOT FULL"),
|
|
0, 0, 0, 0);
|
|
|
|
/* show the current status of the outFifo */
|
|
ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT,
|
|
"OutFifo is %s and %s\n",
|
|
(ixNpeMhConfigOutFifoIsEmpty (npeId) ?
|
|
(int) "EMPTY" : (int) "NOT EMPTY"),
|
|
(ixNpeMhConfigOutFifoIsFull (npeId) ?
|
|
(int) "FULL" : (int) "NOT FULL"),
|
|
0, 0, 0, 0);
|
|
}
|
|
|
|
/*
|
|
* Function definition: ixNpeMhConfigShowReset
|
|
*/
|
|
|
|
void ixNpeMhConfigShowReset (
|
|
IxNpeMhNpeId npeId)
|
|
{
|
|
/* reset the message fifo read counter */
|
|
ixNpeMhConfigStats[npeId].outFifoReads = 0;
|
|
|
|
/* reset the message fifo write counter */
|
|
ixNpeMhConfigStats[npeId].inFifoWrites = 0;
|
|
|
|
/* reset the max inFIFO Full retries counter */
|
|
ixNpeMhConfigStats[npeId].maxInFifoFullRetries = 0;
|
|
|
|
/* reset the max outFIFO empty retries counter */
|
|
ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = 0;
|
|
}
|
|
|
|
|
|
|