upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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517 lines
13 KiB
517 lines
13 KiB
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* Shengzhou Liu <Shengzhou.Liu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <malloc.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/fsl_dtsec.h>
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#include <asm/fsl_serdes.h>
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#include "../common/qixis.h"
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#include "../common/fman.h"
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#include "t2080qds_qixis.h"
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#define EMI_NONE 0xFFFFFFFF
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#define EMI1_RGMII1 0
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#define EMI1_RGMII2 1
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#define EMI1_SLOT1 2
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#define EMI1_SLOT2 6
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#define EMI1_SLOT3 3
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#define EMI1_SLOT4 4
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#define EMI1_SLOT5 5
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#define EMI2 7
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static int mdio_mux[NUM_FM_PORTS];
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static const char * const mdio_names[] = {
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"T2080QDS_MDIO_RGMII1",
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"T2080QDS_MDIO_RGMII2",
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"T2080QDS_MDIO_SLOT1",
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"T2080QDS_MDIO_SLOT3",
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"T2080QDS_MDIO_SLOT4",
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"T2080QDS_MDIO_SLOT5",
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"T2080QDS_MDIO_SLOT2",
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"T2080QDS_MDIO_10GC",
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};
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/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
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static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
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static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
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{
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return mdio_names[muxval];
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}
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struct mii_dev *mii_dev_for_muxval(u8 muxval)
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{
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struct mii_dev *bus;
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const char *name = T2080qds_mdio_name_for_muxval(muxval);
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if (!name) {
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printf("No bus for muxval %x\n", muxval);
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return NULL;
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}
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bus = miiphy_get_dev_by_name(name);
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if (!bus) {
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printf("No bus by name %s\n", name);
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return NULL;
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}
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return bus;
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}
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struct T2080qds_mdio {
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u8 muxval;
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struct mii_dev *realbus;
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};
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static void T2080qds_mux_mdio(u8 muxval)
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{
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u8 brdcfg4;
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if (muxval < 7) {
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
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brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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}
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}
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static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad,
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int regnum)
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{
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struct T2080qds_mdio *priv = bus->priv;
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T2080qds_mux_mdio(priv->muxval);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct T2080qds_mdio *priv = bus->priv;
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T2080qds_mux_mdio(priv->muxval);
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
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}
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static int T2080qds_mdio_reset(struct mii_dev *bus)
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{
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struct T2080qds_mdio *priv = bus->priv;
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return priv->realbus->reset(priv->realbus);
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}
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static int T2080qds_mdio_init(char *realbusname, u8 muxval)
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{
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struct T2080qds_mdio *pmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate T2080QDS MDIO bus\n");
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return -1;
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}
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pmdio = malloc(sizeof(*pmdio));
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if (!pmdio) {
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printf("Failed to allocate T2080QDS private data\n");
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free(bus);
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return -1;
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}
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bus->read = T2080qds_mdio_read;
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bus->write = T2080qds_mdio_write;
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bus->reset = T2080qds_mdio_reset;
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sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval));
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pmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!pmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(pmdio);
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return -1;
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}
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pmdio->muxval = muxval;
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bus->priv = pmdio;
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return mdio_register(bus);
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}
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void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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enum fm_port port, int offset)
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{
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int phy;
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char alias[20];
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struct fixed_link f_link;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
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phy = fm_info_get_phy_address(port);
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switch (port) {
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case FM1_DTSEC1:
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case FM1_DTSEC2:
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case FM1_DTSEC9:
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case FM1_DTSEC10:
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sprintf(alias, "phy_sgmii_s3_%x", phy);
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fdt_set_phy_handle(fdt, compat, addr, alias);
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fdt_status_okay_by_alias(fdt, "emi1_slot3");
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break;
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case FM1_DTSEC5:
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case FM1_DTSEC6:
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if (mdio_mux[port] == EMI1_SLOT1) {
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sprintf(alias, "phy_sgmii_s1_%x", phy);
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fdt_set_phy_handle(fdt, compat, addr, alias);
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fdt_status_okay_by_alias(fdt, "emi1_slot1");
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} else if (mdio_mux[port] == EMI1_SLOT2) {
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sprintf(alias, "phy_sgmii_s2_%x", phy);
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fdt_set_phy_handle(fdt, compat, addr, alias);
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fdt_status_okay_by_alias(fdt, "emi1_slot2");
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}
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break;
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default:
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break;
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}
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} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
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switch (srds_s1) {
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case 0x66: /* XFI interface */
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case 0x6b:
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case 0x6c:
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case 0x6d:
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case 0x71:
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f_link.phy_id = port;
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f_link.duplex = 1;
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f_link.link_speed = 10000;
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f_link.pause = 0;
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f_link.asym_pause = 0;
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/* no PHY for XFI */
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fdt_delprop(fdt, offset, "phy-handle");
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fdt_setprop(fdt, offset, "fixed-link", &f_link,
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sizeof(f_link));
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break;
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default:
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break;
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}
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}
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}
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void fdt_fixup_board_enet(void *fdt)
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{
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return;
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}
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/*
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* This function reads RCW to check if Serdes1{E,F,G,H} is configured
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* as slot 1/2/3 and update the lane_to_slot[] array accordingly
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*/
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static void initialize_lane_to_slot(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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switch (srds_s1) {
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case 0x51:
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case 0x5f:
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case 0x65:
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case 0x6b:
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case 0x71:
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lane_to_slot[5] = 2;
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lane_to_slot[6] = 2;
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lane_to_slot[7] = 2;
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break;
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case 0xa6:
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case 0x8e:
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case 0x8f:
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case 0x82:
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case 0x83:
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case 0xd3:
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case 0xd9:
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case 0xcb:
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lane_to_slot[6] = 2;
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lane_to_slot[7] = 2;
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break;
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case 0xda:
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lane_to_slot[4] = 3;
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lane_to_slot[5] = 3;
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lane_to_slot[6] = 3;
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lane_to_slot[7] = 3;
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break;
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default:
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break;
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}
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}
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_FMAN_ENET)
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int i, idx, lane, slot, interface;
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struct memac_mdio_info dtsec_mdio_info;
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struct memac_mdio_info tgec_mdio_info;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
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u32 srds_s1;
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srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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initialize_lane_to_slot();
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/* Initialize the mdio_mux array so we can recognize empty elements */
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for (i = 0; i < NUM_FM_PORTS; i++)
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mdio_mux[i] = EMI_NONE;
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dtsec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fm_memac_mdio_init(bis, &dtsec_mdio_info);
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tgec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
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tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
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/* Register the 10G MDIO bus */
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fm_memac_mdio_init(bis, &tgec_mdio_info);
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/* Register the muxing front-ends to the MDIO buses */
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T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
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T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
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T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
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T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
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T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
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T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
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T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
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T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
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/* Set the two on-board RGMII PHY address */
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fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
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if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
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FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
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fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
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else
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fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
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switch (srds_s1) {
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case 0x1c:
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case 0x95:
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case 0xa2:
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case 0x94:
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/* SGMII in Slot3 */
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fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
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/* SGMII in Slot2 */
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fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
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break;
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case 0x51:
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case 0x5f:
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case 0x65:
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/* XAUI/HiGig in Slot3 */
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fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
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/* SGMII in Slot2 */
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fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
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break;
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case 0x66:
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/*
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* XFI does not need a PHY to work, but to avoid U-boot use
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* default PHY address which is zero to a MAC when it found
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* a MAC has no PHY address, we give a PHY address to XFI
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* MAC, and should not use a real XAUI PHY address, since
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* MDIO can access it successfully, and then MDIO thinks
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* the XAUI card is used for the XFI MAC, which will cause
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* error.
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*/
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fm_info_set_phy_address(FM1_10GEC1, 4);
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fm_info_set_phy_address(FM1_10GEC2, 5);
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fm_info_set_phy_address(FM1_10GEC3, 6);
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fm_info_set_phy_address(FM1_10GEC4, 7);
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break;
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case 0x6b:
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fm_info_set_phy_address(FM1_10GEC1, 4);
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fm_info_set_phy_address(FM1_10GEC2, 5);
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fm_info_set_phy_address(FM1_10GEC3, 6);
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fm_info_set_phy_address(FM1_10GEC4, 7);
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/* SGMII in Slot2 */
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fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
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break;
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case 0x6c:
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case 0x6d:
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fm_info_set_phy_address(FM1_10GEC1, 4);
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fm_info_set_phy_address(FM1_10GEC2, 5);
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/* SGMII in Slot3 */
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fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
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break;
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case 0x71:
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/* SGMII in Slot3 */
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fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
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/* SGMII in Slot2 */
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fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
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break;
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case 0xa6:
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case 0x8e:
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case 0x8f:
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case 0x82:
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case 0x83:
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/* SGMII in Slot3 */
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fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
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/* SGMII in Slot2 */
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fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
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break;
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case 0xa4:
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case 0x96:
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case 0x8a:
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/* SGMII in Slot3 */
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fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
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break;
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case 0xd9:
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case 0xd3:
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case 0xcb:
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/* SGMII in Slot3 */
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fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
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/* SGMII in Slot2 */
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fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
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break;
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default:
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break;
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}
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
|
|
idx = i - FM1_DTSEC1;
|
|
interface = fm_info_get_enet_if(i);
|
|
switch (interface) {
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
lane = serdes_get_first_lane(FSL_SRDS_1,
|
|
SGMII_FM1_DTSEC1 + idx);
|
|
if (lane < 0)
|
|
break;
|
|
slot = lane_to_slot[lane];
|
|
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
|
|
idx + 1, slot);
|
|
if (QIXIS_READ(present2) & (1 << (slot - 1)))
|
|
fm_disable_port(i);
|
|
|
|
switch (slot) {
|
|
case 1:
|
|
mdio_mux[i] = EMI1_SLOT1;
|
|
fm_info_set_mdio(i, mii_dev_for_muxval(
|
|
mdio_mux[i]));
|
|
break;
|
|
case 2:
|
|
mdio_mux[i] = EMI1_SLOT2;
|
|
fm_info_set_mdio(i, mii_dev_for_muxval(
|
|
mdio_mux[i]));
|
|
break;
|
|
case 3:
|
|
mdio_mux[i] = EMI1_SLOT3;
|
|
fm_info_set_mdio(i, mii_dev_for_muxval(
|
|
mdio_mux[i]));
|
|
break;
|
|
}
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
if (i == FM1_DTSEC3)
|
|
mdio_mux[i] = EMI1_RGMII1;
|
|
else if (i == FM1_DTSEC4 || FM1_DTSEC10)
|
|
mdio_mux[i] = EMI1_RGMII2;
|
|
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
|
|
idx = i - FM1_10GEC1;
|
|
switch (fm_info_get_enet_if(i)) {
|
|
case PHY_INTERFACE_MODE_XGMII:
|
|
if (srds_s1 == 0x51) {
|
|
lane = serdes_get_first_lane(FSL_SRDS_1,
|
|
XAUI_FM1_MAC9 + idx);
|
|
} else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
|
|
lane = serdes_get_first_lane(FSL_SRDS_1,
|
|
HIGIG_FM1_MAC9 + idx);
|
|
} else {
|
|
if (i == FM1_10GEC1 || i == FM1_10GEC2)
|
|
lane = serdes_get_first_lane(FSL_SRDS_1,
|
|
XFI_FM1_MAC9 + idx);
|
|
else
|
|
lane = serdes_get_first_lane(FSL_SRDS_1,
|
|
XFI_FM1_MAC1 + idx);
|
|
}
|
|
|
|
if (lane < 0)
|
|
break;
|
|
mdio_mux[i] = EMI2;
|
|
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
|
|
|
if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
|
|
(srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
|
|
(srds_s1 == 0x71)) {
|
|
/* As XFI is in cage intead of a slot, so
|
|
* ensure doesn't disable the corresponding port
|
|
*/
|
|
break;
|
|
}
|
|
|
|
slot = lane_to_slot[lane];
|
|
if (QIXIS_READ(present2) & (1 << (slot - 1)))
|
|
fm_disable_port(i);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
cpu_eth_init(bis);
|
|
#endif /* CONFIG_FMAN_ENET */
|
|
|
|
return pci_eth_init(bis);
|
|
}
|
|
|