upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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113 lines
3.5 KiB
113 lines
3.5 KiB
/*
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* Advanced Crypto Engine - SHA Firmware
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* Copyright (c) 2012 Samsung Electronics
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <sha256.h>
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#include <sha1.h>
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#include <asm/errno.h>
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#include "ace_sha.h"
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/* SHA1 value for the message of zero length */
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static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
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0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
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0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
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0xAF, 0xD8, 0x07, 0x09};
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/* SHA256 value for the message of zero length */
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static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = {
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0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14,
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0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
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0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C,
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0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55};
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int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len,
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unsigned char *pout, unsigned int hash_type)
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{
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unsigned int i, reg, len;
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unsigned int *pdigest;
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struct exynos_ace_sfr *ace_sha_reg =
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(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
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if (buf_len == 0) {
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/* ACE H/W cannot compute hash value for empty string */
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if (hash_type == ACE_SHA_TYPE_SHA1)
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memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN);
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else
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memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN);
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return 0;
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}
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/* Flush HRDMA */
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writel(ACE_FC_HRDMACFLUSH_ON, &ace_sha_reg->fc_hrdmac);
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writel(ACE_FC_HRDMACFLUSH_OFF, &ace_sha_reg->fc_hrdmac);
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/* Set byte swap of data in */
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writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON,
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&ace_sha_reg->hash_byteswap);
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/* Select Hash input mux as external source */
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reg = readl(&ace_sha_reg->fc_fifoctrl);
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reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT;
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writel(reg, &ace_sha_reg->fc_fifoctrl);
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/* Set Hash as SHA1 or SHA256 and start Hash engine */
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reg = (hash_type == ACE_SHA_TYPE_SHA1) ?
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ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH;
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reg |= ACE_HASH_STARTBIT_ON;
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writel(reg, &ace_sha_reg->hash_control);
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/* Enable FIFO mode */
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writel(ACE_HASH_FIFO_ON, &ace_sha_reg->hash_fifo_mode);
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/* Set message length */
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writel(buf_len, &ace_sha_reg->hash_msgsize_low);
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writel(0, &ace_sha_reg->hash_msgsize_high);
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/* Set HRDMA */
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writel((unsigned int)pbuf, &ace_sha_reg->fc_hrdmas);
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writel(buf_len, &ace_sha_reg->fc_hrdmal);
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while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) ==
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ACE_HASH_MSGDONE_OFF) {
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/*
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* PRNG error bit goes HIGH if a PRNG request occurs without
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* a complete seed setup. We are using this bit to check h/w
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* fault because proper setup is not expected in that case.
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*/
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if ((readl(&ace_sha_reg->hash_status)
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& ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON)
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return -EBUSY;
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}
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/* Clear MSG_DONE bit */
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writel(ACE_HASH_MSGDONE_ON, &ace_sha_reg->hash_status);
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/* Read hash result */
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pdigest = (unsigned int *)pout;
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len = (hash_type == ACE_SHA_TYPE_SHA1) ? SHA1_SUM_LEN : SHA256_SUM_LEN;
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for (i = 0; i < len / 4; i++)
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pdigest[i] = readl(&ace_sha_reg->hash_result[i]);
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/* Clear HRDMA pending bit */
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writel(ACE_FC_HRDMA, &ace_sha_reg->fc_intpend);
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return 0;
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}
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void hw_sha256(const unsigned char *pbuf, unsigned int buf_len,
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unsigned char *pout, unsigned int chunk_size)
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{
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if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA256))
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debug("ACE was not setup properly or it is faulty\n");
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}
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void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
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unsigned char *pout, unsigned int chunk_size)
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{
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if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
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debug("ACE was not setup properly or it is faulty\n");
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}
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