upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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68 lines
4.0 KiB
68 lines
4.0 KiB
/* DO NOT EDIT THIS FILE
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* Automatically generated by generate-cdef-headers.xsl
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* DO NOT EDIT THIS FILE
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*/
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#ifndef __BFIN_CDEF_ADSP_BF514_proc__
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#define __BFIN_CDEF_ADSP_BF514_proc__
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#include "BF512_cdef.h"
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#define bfin_read_RSI_PWR_CONTROL() bfin_read16(RSI_PWR_CONTROL)
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#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val)
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#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL)
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#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
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#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
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#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
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#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
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#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
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#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
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#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
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#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
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#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
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#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
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#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
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#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
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#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
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#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
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#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
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#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
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#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
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#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
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#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
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#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL)
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#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
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#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
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#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
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#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
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#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
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#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL)
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#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val)
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#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
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#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
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#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
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#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
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#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
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#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
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#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
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#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
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#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
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#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
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#define bfin_read_RSI_ESTAT() bfin_read16(RSI_ESTAT)
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#define bfin_write_RSI_ESTAT(val) bfin_write16(RSI_ESTAT, val)
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#define bfin_read_RSI_EMASK() bfin_read16(RSI_EMASK)
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#define bfin_write_RSI_EMASK(val) bfin_write16(RSI_EMASK, val)
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#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG)
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#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val)
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#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
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#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
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#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
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#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
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#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
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#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
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#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
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#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
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#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
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#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
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#endif /* __BFIN_CDEF_ADSP_BF514_proc__ */
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