upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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432 lines
15 KiB
432 lines
15 KiB
/*
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* (C) Copyright 2008
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* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
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*
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* based on the Sequoia board configuration by
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* Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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**********************************************************************
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* DU440.h - configuration for esd's DU440 board (Power PC440EPx)
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**********************************************************************
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_DU440 1 /* Board is esd DU440 */
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#define CONFIG_440EPX 1 /* Specific PPC440EPx */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
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#endif
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
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#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */
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#define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */
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#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
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#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
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#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
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#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
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#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
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#define CONFIG_SYS_PCI_IOBASE 0xe8000000
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
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#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */
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#define CONFIG_SYS_USB2D0_BASE 0xe0000100
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#define CONFIG_SYS_USB_DEVICE 0xe0000000
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#define CONFIG_SYS_USB_HOST 0xe0000400
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/*
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* Initial RAM & stack pointer
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*/
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/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
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#define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
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#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI 1
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*
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* Video Port
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*/
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_SMI_LYNXEM
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SPLASH_SCREEN_ALIGN
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#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
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#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
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/*
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* FLASH related
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*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif
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#ifdef CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_ENV_OFFSET 0 /* environment starts at */
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/* the beginning of the EEPROM */
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#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
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#endif
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/*
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* DDR SDRAM
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*/
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#define CONFIG_SYS_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
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/* 440EPx errata CHIP 11 */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#define CONFIG_DDR_ECC /* Use ECC when available */
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#define SPD_EEPROM_ADDRESS {0x50}
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#define CONFIG_PROG_SDRAM_TLB
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/*
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* I2C
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
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#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_I2C_MULTI_BUS 1
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define IIC1_MCP3021_ADDR 0x4d
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#define IIC1_USB2507_ADDR 0x2c
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#ifdef CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
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#endif
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#define CONFIG_SYS_I2C_MULTI_EEPROMS
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
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#define CONFIG_SYS_EEPROM_WREN 1
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#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
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/*
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* standard dtt sensor configuration - bottom bit will determine local or
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* remote sensor of the TMP401
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*/
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#define CONFIG_DTT_SENSORS { 0, 1 }
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/*
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* The PMC440 uses a TI TMP401 temperature sensor. This part
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* is basically compatible to the ADM1021 that is supported
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* by U-Boot.
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*
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* - i2c addr 0x4c
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* - conversion rate 0x02 = 0.25 conversions/second
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* - ALERT ouput disabled
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* - local temp sensor enabled, min set to 0 deg, max set to 70 deg
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* - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
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*/
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#define CONFIG_DTT_ADM1021
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#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
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/*
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* RTC stuff
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*/
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#define CONFIG_RTC_DS1338
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"ethrotate=no\0" \
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"hostname=du440\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_self=run ramargs addip addtty optargs;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
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"bootm\0" \
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"rootpath=/tftpboot/du440/target_root_du440\0" \
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"img=/tftpboot/du440/uImage\0" \
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"kernel_addr=FFC00000\0" \
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"ramdisk_addr=FFE00000\0" \
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"initrd_high=30000000\0" \
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"load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
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"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
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"cp.b 100000 FFFA0000 60000\0" \
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""
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#define CONFIG_PREBOOT /* enable preboot variable */
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#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#ifndef __ASSEMBLY__
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int du440_phy_addr(int devnum);
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#endif
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#undef CONFIG_PHY_GIGE /* no GbE detection */
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#define CONFIG_HAS_ETH0
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#define CONFIG_SYS_RX_ETH_BUFFER 128
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR du440_phy_addr(1)
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/*
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* USB
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*/
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_USB_STORAGE
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#define CONFIG_SYS_OHCI_BE_CONTROLLER
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "du440"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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/* Comment this out to enable USB 1.1 device */
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#define USB_2_0_DEVICE
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_BMP
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_DTT
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_SOURCE
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#define CONFIG_CMD_USB
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#define CONFIG_SUPPORT_VFAT
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CONFIG_AUTOBOOT_KEYED 1
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press SPACE to abort autoboot in %d seconds\n", bootdelay
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#define CONFIG_AUTOBOOT_DELAY_STR "d"
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#define CONFIG_AUTOBOOT_STOP_STR " "
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/*
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* PCI stuff
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*/
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
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/* Board-specific PCI */
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#define CONFIG_SYS_PCI_TARGET_INIT
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#define CONFIG_SYS_PCI_MASTER_INIT
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* External Bus Controller (EBC) Setup
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*/
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#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CPLD_BASE 0xC0000000
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#define CONFIG_SYS_CPLD_RANGE 0x00000010
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#define CONFIG_SYS_DUMEM_BASE 0xC0100000
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#define CONFIG_SYS_DUMEM_RANGE 0x00100000
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#define CONFIG_SYS_DUIO_BASE 0xC0200000
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#define CONFIG_SYS_DUIO_RANGE 0x00010000
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#define CONFIG_SYS_NAND0_CS 2 /* NAND chip connected to CSx */
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#define CONFIG_SYS_NAND1_CS 3 /* NAND chip connected to CSx */
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x04017200
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#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
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/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
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#define CONFIG_SYS_EBC_PB1AP 0x018003c0
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#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
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/* Memory Bank 2 (NAND-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB2AP 0x018003c0
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#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND0_ADDR | 0x1c000)
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/* Memory Bank 3 (NAND-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB3AP 0x018003c0
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#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND1_ADDR | 0x1c000)
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/* Memory Bank 4 (DUMEM, 1MB) initialization */
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#define CONFIG_SYS_EBC_PB4AP 0x018053c0
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#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_DUMEM_BASE | 0x18000)
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/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
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#define CONFIG_SYS_EBC_PB5AP 0x018053c0
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#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_DUIO_BASE | 0x18000)
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/*
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* NAND FLASH
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*/
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#define CONFIG_SYS_MAX_NAND_DEVICE 2
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#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
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CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#define CONFIG_SOURCE 1
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#endif /* __CONFIG_H */
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