upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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454 lines
16 KiB
454 lines
16 KiB
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC824X 1
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/* #define CONFIG_MPC8240 1 */
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#define CONFIG_MPC8245 1
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#define CONFIG_EXALION 1
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#if defined (CONFIG_MPC8240)
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/* #warning ---------- eXalion with MPC8240 --------------- */
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#elif defined (CONFIG_MPC8245)
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/* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */
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#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
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#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
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#else
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#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
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#endif
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/* older kernels need clock in MHz newer in Hz */
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/* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */
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#undef CONFIG_CLOCKS_IN_MHZ
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#define CONFIG_BOOTDELAY 10
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/*#define CONFIG_DRAM_SPEED 66 */ /* MHz */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_PCI
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_MISC_INIT_R 1
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */
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/* return real value. */
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#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
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#undef CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area
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*/
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#define CONFIG_SYS_INIT_DATA_SIZE 128
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#if defined (CONFIG_MPC8240)
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#define CONFIG_SYS_FLASH_BASE 0xFFE00000
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#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */
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#elif defined (CONFIG_MPC8245)
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#define CONFIG_SYS_FLASH_BASE 0xFFC00000
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#define CONFIG_SYS_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */
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#else
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#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
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#endif
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */
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#define CONFIG_ENV_ADDR 0xFFFC0000
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#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
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#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
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#define CONFIG_SYS_EUMB_ADDR 0xFC000000
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/* #define CONFIG_SYS_ISA_MEM 0xFD000000 */
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#define CONFIG_SYS_ISA_IO 0xFE000000
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE
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#define FLASH_BASE1_PRELIM 0
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*/
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#define CONFIG_PCI 1 /* include pci support */
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#undef CONFIG_PCI_PNP
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#define CONFIG_EEPRO100 1
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#define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */
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#define PCI_ENET0_IOADDR 0x80000000
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#define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */
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#define PCI_ENET1_IOADDR 0x81000000
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#define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */
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#define PCI_ENET2_IOADDR 0x82000000
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#define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */
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#define PCI_ENET3_IOADDR 0x83000000
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/*-----------------------------------------------------------------------
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550 1
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#define CONFIG_SYS_NS16550_SERIAL 1
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#if (CONFIG_CONS_INDEX == 1)
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#define CONFIG_SYS_NS16550_CLK 1843200 /* COM1 only ! */
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#else
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#define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
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#endif
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + 0x3F8)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500)
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#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4600)
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/*-----------------------------------------------------------------------
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* select i2c support configuration
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*
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* Supported configurations are {none, software, hardware} drivers.
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* If the software driver is chosen, there are some additional
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* configuration items that the driver uses to drive the port pins.
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*/
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#define CONFIG_HARD_I2C 1 /* To enable I2C support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*-----------------------------------------------------------------------
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
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/*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */
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#if defined (CONFIG_MPC8245)
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/* Bit-field values for PMCR2. */
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#if defined (CONFIG_133MHZ_DRAM)
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#define CONFIG_SYS_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */
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#define CONFIG_SYS_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */
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#endif
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/* Bit-field values for MIOCR1. */
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#if !defined (CONFIG_133MHZ_DRAM)
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#define CONFIG_SYS_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */
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#endif
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/* Bit-field values for MIOCR2. */
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#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */
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/* - note bottom 3 bits MUST be 0 */
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#endif
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/* Bit-field values for MCCR1. */
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#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
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#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
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/* Bit-field values for MCCR2. */
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#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
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#if defined (CONFIG_133MHZ_DRAM)
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#define CONFIG_SYS_REFINT 1300 /* no of clock cycles between CBR */
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#else /* refresh cycles */
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#define CONFIG_SYS_REFINT 750
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#endif
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/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
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#if defined (CONFIG_133MHZ_DRAM)
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#define CONFIG_SYS_BSTOPRE 1023
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#else
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#define CONFIG_SYS_BSTOPRE 250
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#endif
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/* Bit-field values for MCCR3. */
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/* the following are for SDRAM only */
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#if defined (CONFIG_133MHZ_DRAM)
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#define CONFIG_SYS_REFREC 9 /* Refresh to activate interval */
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#else
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#define CONFIG_SYS_REFREC 5 /* Refresh to activate interval */
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#endif
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#if defined (CONFIG_MPC8240)
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#define CONFIG_SYS_RDLAT 2 /* data latency from read command */
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#endif
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/* Bit-field values for MCCR4. */
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#if defined (CONFIG_133MHZ_DRAM)
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#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
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#define CONFIG_SYS_ACTTOPRE 7 /* Activate to Precharge interval */
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#define CONFIG_SYS_ACTORW 5 /* Activate to R/W */
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#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
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#else
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#if 0
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#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
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#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */
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#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
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#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
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#endif
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#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
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#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
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#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
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#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
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#endif
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#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
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#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
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#define CONFIG_SYS_REGDIMM 0
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#if defined (CONFIG_MPC8240)
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#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 0
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#elif defined (CONFIG_MPC8245)
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#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
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#define CONFIG_SYS_EXTROM 0
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#else
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#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
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#endif
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/*-----------------------------------------------------------------------
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memory bank settings
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* only bits 20-29 are actually used from these vales to set the
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* start/end address the upper two bits will be 0, and the lower 20
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* bits will be set to 0x00000 for a start address, or 0xfffff for an
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* end address
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*/
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#define CONFIG_SYS_BANK0_START 0x00000000
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#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
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#define CONFIG_SYS_BANK0_ENABLE 1
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#define CONFIG_SYS_BANK1_START 0x3ff00000
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#define CONFIG_SYS_BANK1_END 0x3fffffff
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#define CONFIG_SYS_BANK1_ENABLE 0
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#define CONFIG_SYS_BANK2_START 0x3ff00000
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#define CONFIG_SYS_BANK2_END 0x3fffffff
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#define CONFIG_SYS_BANK2_ENABLE 0
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#define CONFIG_SYS_BANK3_START 0x3ff00000
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#define CONFIG_SYS_BANK3_END 0x3fffffff
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#define CONFIG_SYS_BANK3_ENABLE 0
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#define CONFIG_SYS_BANK4_START 0x00000000
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#define CONFIG_SYS_BANK4_END 0x00000000
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#define CONFIG_SYS_BANK4_ENABLE 0
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#define CONFIG_SYS_BANK5_START 0x00000000
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#define CONFIG_SYS_BANK5_END 0x00000000
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#define CONFIG_SYS_BANK5_ENABLE 0
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#define CONFIG_SYS_BANK6_START 0x00000000
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#define CONFIG_SYS_BANK6_END 0x00000000
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#define CONFIG_SYS_BANK6_ENABLE 0
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#define CONFIG_SYS_BANK7_START 0x00000000
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#define CONFIG_SYS_BANK7_END 0x00000000
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#define CONFIG_SYS_BANK7_ENABLE 0
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/*-----------------------------------------------------------------------
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* Memory bank enable bitmask, specifying which of the banks defined above
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are actually present. MSB is for bank #7, LSB is for bank #0.
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*/
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#define CONFIG_SYS_BANK_ENABLE 0x01
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#if defined (CONFIG_MPC8240)
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#define CONFIG_SYS_ODCR 0xDF /* configures line driver impedances, */
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/* see 8240 book for bit definitions */
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#elif defined (CONFIG_MPC8245)
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#if defined (CONFIG_133MHZ_DRAM)
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#define CONFIG_SYS_ODCR 0xFE /* configures line driver impedances - 133MHz */
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#else
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#define CONFIG_SYS_ODCR 0xDE /* configures line driver impedances - 66MHz */
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#endif
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#else
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#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
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#endif
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#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
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/* currently accessed page in memory */
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/* see 8240 book for details */
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/*-----------------------------------------------------------------------
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* Block Address Translation (BAT) register settings.
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*/
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/* SDRAM 0 - 256MB */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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/* stack in DCACHE @ 1GB (no backing mem) */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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/* PCI memory */
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#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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/* Flash, config addrs, etc */
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#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/* values according to the manual */
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#define CONFIG_DRAM_50MHZ 1
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#define CONFIG_SDRAM_50MHZ
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#undef NR_8259_INTS
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#define NR_8259_INTS 1
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff
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*/
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
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#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */
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#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO /* base address */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
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#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
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#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
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#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
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#define CONFIG_ATAPI
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#undef CONFIG_IDE_RESET /* reset for ide supported... */
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#undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
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/*-----------------------------------------------------------------------
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* DISK Partition support
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*/
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#define CONFIG_DOS_PARTITION
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/*-----------------------------------------------------------------------
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#endif /* __CONFIG_H */
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