upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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128 lines
3.0 KiB
128 lines
3.0 KiB
/*
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* (C) Copyright 2003
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* Texas Instruments <www.ti.com>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* (C) Copyright 2002-2004
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* (C) Copyright 2004
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* Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct davinci_timer {
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u_int32_t pid12;
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u_int32_t emumgt;
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u_int32_t na1;
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u_int32_t na2;
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u_int32_t tim12;
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u_int32_t tim34;
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u_int32_t prd12;
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u_int32_t prd34;
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u_int32_t tcr;
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u_int32_t tgcr;
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u_int32_t wdtcr;
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};
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static struct davinci_timer * const timer =
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(struct davinci_timer *)CONFIG_SYS_TIMERBASE;
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#define TIMER_LOAD_VAL 0xffffffff
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#define TIM_CLK_DIV 16
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int timer_init(void)
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{
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/* We are using timer34 in unchained 32-bit mode, full speed */
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writel(0x0, &timer->tcr);
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writel(0x0, &timer->tgcr);
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writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
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writel(0x0, &timer->tim34);
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writel(TIMER_LOAD_VAL, &timer->prd34);
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writel(2 << 22, &timer->tcr);
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gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
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gd->timer_reset_value = 0;
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return(0);
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}
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void reset_timer(void)
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{
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gd->timer_reset_value = get_ticks();
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}
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/*
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* Get the current 64 bit timer tick count
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*/
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unsigned long long get_ticks(void)
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{
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unsigned long now = readl(&timer->tim34);
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/* increment tbu if tbl has rolled over */
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if (now < gd->tbl)
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gd->tbu++;
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gd->tbl = now;
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return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
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}
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ulong get_timer(ulong base)
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{
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unsigned long long timer_diff;
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timer_diff = get_ticks() - gd->timer_reset_value;
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return (timer_diff / (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
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}
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void __udelay(unsigned long usec)
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{
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unsigned long long endtime;
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endtime = ((unsigned long long)usec * gd->timer_rate_hz) / 1000000UL;
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endtime += get_ticks();
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while (get_ticks() < endtime)
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;
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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