upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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132 lines
3.2 KiB
132 lines
3.2 KiB
/*
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* (C) Copyright 2011
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Lei Wen <leiwen@marvell.com>,
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/arch/pantheon.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Pantheon DRAM controller supports upto 8 banks
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* for chip select 0 and 1
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*/
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/*
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* DDR Memory Control Registers
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* Refer Datasheet 4.4
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*/
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struct panthddr_map_registers {
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u32 cs; /* Memory Address Map Register -CS */
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u32 pad[3];
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};
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struct panthddr_registers {
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u8 pad[0x100 - 0x000];
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struct panthddr_map_registers mmap[2];
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};
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/*
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* panth_sdram_base - reads SDRAM Base Address Register
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*/
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u32 panth_sdram_base(int chip_sel)
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{
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struct panthddr_registers *ddr_regs =
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(struct panthddr_registers *)PANTHEON_DRAM_BASE;
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u32 result = 0;
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u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
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if (!CS_valid)
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return 0;
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result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
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return result;
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}
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/*
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* panth_sdram_size - reads SDRAM size
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*/
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u32 panth_sdram_size(int chip_sel)
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{
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struct panthddr_registers *ddr_regs =
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(struct panthddr_registers *)PANTHEON_DRAM_BASE;
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u32 result = 0;
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u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
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if (!CS_valid)
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return 0;
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result = readl(&ddr_regs->mmap[chip_sel].cs);
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result = (result >> 16) & 0xF;
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if (result < 0x7) {
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printf("Unknown DRAM Size\n");
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return -1;
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} else {
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return ((0x8 << (result - 0x7)) * 1024 * 1024);
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}
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}
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#ifndef CONFIG_SYS_BOARD_DRAM_INIT
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int dram_init(void)
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{
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int i;
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gd->ram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = panth_sdram_base(i);
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gd->bd->bi_dram[i].size = panth_sdram_size(i);
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/*
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* It is assumed that all memory banks are consecutive
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* and without gaps.
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* If the gap is found, ram_size will be reported for
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* consecutive memory only
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*/
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if (gd->bd->bi_dram[i].start != gd->ram_size)
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break;
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gd->ram_size += gd->bd->bi_dram[i].size;
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}
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for (; i < CONFIG_NR_DRAM_BANKS; i++) {
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/*
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* If above loop terminated prematurely, we need to set
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* remaining banks' start address & size as 0. Otherwise other
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* u-boot functions and Linux kernel gets wrong values which
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* could result in crash
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*/
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gd->bd->bi_dram[i].start = 0;
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gd->bd->bi_dram[i].size = 0;
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}
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return 0;
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}
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/*
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* If this function is not defined here,
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* board.c alters dram bank zero configuration defined above.
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*/
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void dram_init_banksize(void)
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{
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dram_init();
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}
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#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
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