upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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57 lines
1.4 KiB
57 lines
1.4 KiB
/*
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* Adaptive Body Bias programming sequence for OMAP5 family
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*
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* (C) Copyright 2013
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* Texas Instruments, <www.ti.com>
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*
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* Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/omap_common.h>
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#include <asm/io.h>
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/*
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* Setup LDOVBB for OMAP5.
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* On OMAP5+ some ABB settings are fused. They are handled
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* in the following way:
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*
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* 1. corresponding EFUSE register contains ABB enable bit
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* and VSET value
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* 2. If ABB enable bit is set to 1, than ABB should be
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* enabled, otherwise ABB should be disabled
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* 3. If ABB is enabled, than VSET value should be copied
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* to corresponding MUX control register
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*/
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s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
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{
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u32 vset;
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u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK;
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u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK;
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if (!is_omap54xx()) {
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/* DRA7 */
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fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK;
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fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK;
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}
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/*
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* ABB parameters must be properly fused
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* otherwise ABB should be disabled
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*/
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vset = readl(fuse);
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if (!(vset & fuse_enable_mask))
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return -1;
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/* prepare VSET value for LDOVBB mux register */
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vset &= fuse_vset_mask;
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vset >>= ffs(fuse_vset_mask) - 1;
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vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
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vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
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/* setup LDOVBB using fused value */
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clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset);
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return 0;
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}
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