upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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317 lines
8.5 KiB
317 lines
8.5 KiB
/*
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* (C) Copyright 2001
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* Paul Geerinckx
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include "atm.h"
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#include <i2c.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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/* used PLD registers */
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# define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
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# define PLD_EXT_RES (unsigned char *) (0x10000000 + 10)
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# define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
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# define PLD_EXT_LED (unsigned char *) (0x10000000 + 12)
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# define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13)
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] =
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{
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
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_NOT_USED_,
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0xFFFAF834, 0xFFE5B435, /* last */
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_NOT_USED_,
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
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0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
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0xF1AAF804, 0xFFA5F447, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
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0xFFAFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* MRS sequence (Offset 38 in UPMA RAM)
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*/
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0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */
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_NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0xFFAFFC04, 0xFFAFFC05, /* last */
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_NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile iop8xx_t *iop = &immap->im_ioport;
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volatile fec_t *fecp = &immap->im_cpm.cp_fec;
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long int size;
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upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or2 = CFG_OR2_PRELIM;
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memctl->memc_br2 = CFG_BR2_PRELIM;
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memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
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udelay(200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
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udelay(1);
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memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
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udelay(1);
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memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
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udelay(1);
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memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
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udelay(1);
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memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
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udelay(1);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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*/
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size = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
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udelay (1000);
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memctl->memc_mamr = CFG_MAMR;
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udelay (1000);
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/*
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* Final mapping
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*/
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memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
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memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
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udelay(10000);
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/* prepare pin multiplexing for fast ethernet */
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atmLoad();
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fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
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iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
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return (size);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base, long int maxsize)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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memctl->memc_mamr = mamr_value;
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for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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return (cnt * sizeof(long));
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}
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}
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return (maxsize);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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return (0);
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}
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void board_serial_init(void)
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{
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;/* nothing to do here */
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}
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void board_ether_init(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile iop8xx_t *iop = &immap->im_ioport;
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volatile fec_t *fecp = &immap->im_cpm.cp_fec;
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atmLoad();
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fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
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iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
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}
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int board_pre_init (void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile iop8xx_t *iop = &immap->im_ioport;
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/* configure the LED timing output pins - port A pin 4 */
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iop->iop_papar = 0x0800;
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iop->iop_padir = 0x0800;
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/* start timer 2 for the 4hz LED blink rate */
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timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */
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timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
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timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
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/* chip select for PLD access */
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memctl->memc_br6 = 0x10000401;
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memctl->memc_or6 = 0xFC000908;
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/* PLD initial values ( set LEDs, remove reset on LXT) */
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*PLD_GCR1_REG = 0x06;
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*PLD_EXT_RES = 0xC0;
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*PLD_EXT_FETH = 0x40;
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*PLD_EXT_LED = 0xFF;
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*PLD_EXT_X21 = 0x04;
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return 0;
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}
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void board_get_enetaddr (uchar *addr)
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{
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int i;
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile cpm8xx_t *cpm = &immap->im_cpm;
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unsigned int rccrtmp;
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char default_mac_addr[] = {0x00, 0x08, 0x01, 0x02, 0x03, 0x04};
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for (i=0; i<6; i++)
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addr[i] = default_mac_addr[i];
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printf("There is an error in the i2c driver .. /n");
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printf("You need to fix it first....../n");
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rccrtmp = cpm->cp_rccr;
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cpm->cp_rccr |= 0x0020;
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i2c_reg_read(0xa0, 0);
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printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
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i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0),
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i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0) );
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cpm->cp_rccr = rccrtmp;
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}
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