upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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41 lines
1.4 KiB
41 lines
1.4 KiB
/*
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* (C) Copyright 2007
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* Michael Schwingen, michael@schwingen.org
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*
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* hardware register definitions for the AcTux-1 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ACTUX1_HW_H
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#define _ACTUX1_HW_H
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/* 0 = LED off,1 = green, 2 = red, 3 = orange */
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#define ACTUX1_LED1(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
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#define ACTUX1_LED2(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
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#define ACTUX1_LED3(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
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#define ACTUX1_LED4(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
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#define ACTUX1_LED5(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
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#define ACTUX1_LED6(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
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#define ACTUX1_LED7(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
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#define ACTUX1_HS(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
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#define ACTUX1_HS_DCD 0x01
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#define ACTUX1_HS_DSR 0x02
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#define ACTUX1_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS
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#define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
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/* GPIO settings */
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#define CONFIG_SYS_GPIO_PCI1_INTA 2
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#define CONFIG_SYS_GPIO_PCI2_INTA 3
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#define CONFIG_SYS_GPIO_I2C_SDA 4
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#define CONFIG_SYS_GPIO_I2C_SCL 5
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#define CONFIG_SYS_GPIO_DBGJUMPER 9
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#define CONFIG_SYS_GPIO_BUTTON1 10
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#define CONFIG_SYS_GPIO_DBGSENSE 11
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#define CONFIG_SYS_GPIO_DTR 12
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#define CONFIG_SYS_GPIO_IORST 13 /* Out */
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#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
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#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
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#endif
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