upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
101 lines
2.5 KiB
101 lines
2.5 KiB
/*
|
|
* Copyright (C) 2009 Pegatron Corporation
|
|
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
|
* Copyright (C) 2009-2012 Genesi USA, Inc.
|
|
*
|
|
* BASED ON: imx51evk
|
|
*
|
|
* (C) Copyright 2009
|
|
* Stefano Babic DENX Software Engineering sbabic@denx.de.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
/*
|
|
* Boot Device : one of
|
|
* spi, sd (the board has no nand neither onenand)
|
|
*/
|
|
BOOT_FROM spi
|
|
|
|
/*
|
|
* Device Configuration Data (DCD)
|
|
*
|
|
* Each entry must have the format:
|
|
* Addr-type Address Value
|
|
*
|
|
* where:
|
|
* Addr-type register length (1,2 or 4 bytes)
|
|
* Address absolute address of the register
|
|
* value value to be stored in the register
|
|
*/
|
|
/* DDR bus IOMUX PAD settings */
|
|
DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
|
|
DATA 4 0x73fa850c 0x20c5 # SDODT1
|
|
DATA 4 0x73fa8510 0x20c5 # SDODT0
|
|
DATA 4 0x73fa8848 0x4 # DDR_A1
|
|
DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK
|
|
DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0
|
|
DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1
|
|
DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2
|
|
DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3
|
|
DATA 4 0x73fa8820 0x0 # DDRPKS
|
|
DATA 4 0x73fa84ac 0xe5 # SDWE
|
|
DATA 4 0x73fa84b0 0xe5 # SDCKE0
|
|
DATA 4 0x73fa84b4 0xe5 # SDCKE1
|
|
DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
|
|
DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
|
|
|
|
/*
|
|
* Setting DDR for micron
|
|
* 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
|
|
* CAS=3 BL=4
|
|
*/
|
|
/* ESDCTL_ESDCTL0 */
|
|
DATA 4 0x83fd9000 0x82a20000
|
|
/* ESDCTL_ESDCTL1 */
|
|
DATA 4 0x83fd9008 0x82a20000
|
|
/* ESDCTL_ESDMISC */
|
|
DATA 4 0x83fd9010 0xcaaaf6d0
|
|
/* ESDCTL_ESDCFG0 */
|
|
DATA 4 0x83fd9004 0x333574aa
|
|
/* ESDCTL_ESDCFG1 */
|
|
DATA 4 0x83fd900c 0x333574aa
|
|
|
|
/* Init DRAM on CS0 */
|
|
/* ESDCTL_ESDSCR */
|
|
DATA 4 0x83fd9014 0x04008008
|
|
DATA 4 0x83fd9014 0x0000801a
|
|
DATA 4 0x83fd9014 0x0000801b
|
|
DATA 4 0x83fd9014 0x00448019
|
|
DATA 4 0x83fd9014 0x07328018
|
|
DATA 4 0x83fd9014 0x04008008
|
|
DATA 4 0x83fd9014 0x00008010
|
|
DATA 4 0x83fd9014 0x00008010
|
|
DATA 4 0x83fd9014 0x06328018
|
|
DATA 4 0x83fd9014 0x03808019
|
|
DATA 4 0x83fd9014 0x00408019
|
|
DATA 4 0x83fd9014 0x00008000
|
|
|
|
/* Init DRAM on CS1 */
|
|
DATA 4 0x83fd9014 0x0400800c
|
|
DATA 4 0x83fd9014 0x0000801e
|
|
DATA 4 0x83fd9014 0x0000801f
|
|
DATA 4 0x83fd9014 0x0000801d
|
|
DATA 4 0x83fd9014 0x0732801c
|
|
DATA 4 0x83fd9014 0x0400800c
|
|
DATA 4 0x83fd9014 0x00008014
|
|
DATA 4 0x83fd9014 0x00008014
|
|
DATA 4 0x83fd9014 0x0632801c
|
|
DATA 4 0x83fd9014 0x0380801d
|
|
DATA 4 0x83fd9014 0x0042801d
|
|
DATA 4 0x83fd9014 0x00008004
|
|
|
|
/* Write to CTL0 */
|
|
DATA 4 0x83fd9000 0xb2a20000
|
|
/* Write to CTL1 */
|
|
DATA 4 0x83fd9008 0xb2a20000
|
|
/* ESDMISC */
|
|
DATA 4 0x83fd9010 0xcaaaf6d0
|
|
/* ESDCTL_ESDCDLYGD */
|
|
DATA 4 0x83fd9034 0x90000000
|
|
DATA 4 0x83fd9014 0x00000000
|
|
|