upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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275 lines
6.6 KiB
275 lines
6.6 KiB
/*
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* (C) Copyright 2001
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* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <i2c.h>
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int sysControlDisplay(int digit, uchar ascii_code);
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extern void Plx9030Init(void);
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extern void SPD67290Init(void);
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/* We have to clear the initial data area here. Couldn't have done it
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* earlier because DRAM had not been initialized.
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*/
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int board_early_init_f(void)
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{
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/* enable DUAL UART Mode on CPC45 */
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*(uchar*)DUART_DCR |= 0x1; /* set DCM bit */
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return 0;
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}
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int checkboard(void)
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{
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/*
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char revision = BOARD_REV;
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*/
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ulong busfreq = get_bus_freq(0);
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char buf[32];
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puts ("CPC45 ");
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/*
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printf("Revision %d ", revision);
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*/
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printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
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return 0;
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}
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phys_size_t initdram (int board_type)
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{
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int m, row, col, bank, i, ref;
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unsigned long start, end;
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uint32_t mccr1, mccr2;
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uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
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uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
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uint8_t mber = 0;
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unsigned int tmp;
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i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
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if (i2c_reg_read (0x50, 2) != 0x04)
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return 0; /* Memory type */
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m = i2c_reg_read (0x50, 5); /* # of physical banks */
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row = i2c_reg_read (0x50, 3); /* # of rows */
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col = i2c_reg_read (0x50, 4); /* # of columns */
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bank = i2c_reg_read (0x50, 17); /* # of logical banks */
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ref = i2c_reg_read (0x50, 12); /* refresh rate / type */
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CONFIG_READ_WORD(MCCR1, mccr1);
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mccr1 &= 0xffff0000;
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CONFIG_READ_WORD(MCCR2, mccr2);
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mccr2 &= 0xffff0000;
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start = CFG_SDRAM_BASE;
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end = start + (1 << (col + row + 3) ) * bank - 1;
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for (i = 0; i < m; i++) {
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mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
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if (i < 4) {
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msar1 |= ((start >> 20) & 0xff) << i * 8;
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emsar1 |= ((start >> 28) & 0xff) << i * 8;
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mear1 |= ((end >> 20) & 0xff) << i * 8;
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emear1 |= ((end >> 28) & 0xff) << i * 8;
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} else {
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msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
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emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
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mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
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emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
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}
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mber |= 1 << i;
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start += (1 << (col + row + 3) ) * bank;
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end += (1 << (col + row + 3) ) * bank;
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}
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for (; i < 8; i++) {
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if (i < 4) {
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msar1 |= 0xff << i * 8;
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emsar1 |= 0x30 << i * 8;
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mear1 |= 0xff << i * 8;
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emear1 |= 0x30 << i * 8;
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} else {
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msar2 |= 0xff << (i-4) * 8;
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emsar2 |= 0x30 << (i-4) * 8;
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mear2 |= 0xff << (i-4) * 8;
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emear2 |= 0x30 << (i-4) * 8;
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}
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}
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switch(ref) {
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case 0x00:
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case 0x80:
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tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
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break;
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case 0x01:
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case 0x81:
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tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
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break;
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case 0x02:
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case 0x82:
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tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
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break;
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case 0x03:
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case 0x83:
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tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
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break;
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case 0x04:
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case 0x84:
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tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
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break;
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case 0x05:
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case 0x85:
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tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
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break;
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default:
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tmp = 0x512;
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break;
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}
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CONFIG_WRITE_WORD(MCCR1, mccr1);
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CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
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CONFIG_WRITE_WORD(MSAR1, msar1);
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CONFIG_WRITE_WORD(EMSAR1, emsar1);
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CONFIG_WRITE_WORD(MEAR1, mear1);
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CONFIG_WRITE_WORD(EMEAR1, emear1);
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CONFIG_WRITE_WORD(MSAR2, msar2);
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CONFIG_WRITE_WORD(EMSAR2, emsar2);
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CONFIG_WRITE_WORD(MEAR2, mear2);
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CONFIG_WRITE_WORD(EMEAR2, emear2);
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CONFIG_WRITE_BYTE(MBER, mber);
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return (1 << (col + row + 3) ) * bank * m;
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}
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/*
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* Initialize PCI Devices, report devices found.
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*/
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static struct pci_config_table pci_cpc45_config_table[] = {
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#ifndef CONFIG_PCI_PNP
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
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PCI_PLX9030_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCMCIA_IO_BASE,
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PCMCIA_IO_BASE,
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PCI_COMMAND_MEMORY | PCI_COMMAND_IO }},
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#endif /*CONFIG_PCI_PNP*/
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{ }
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};
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struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_cpc45_config_table,
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#endif
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};
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void pci_init_board(void)
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{
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pci_mpc824x_init(&hose);
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/* init PCI_to_LOCAL Bus BRIDGE */
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Plx9030Init();
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/* Clear Display */
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DISP_CWORD = 0x0;
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sysControlDisplay(0,' ');
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sysControlDisplay(1,'C');
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sysControlDisplay(2,'P');
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sysControlDisplay(3,'C');
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sysControlDisplay(4,' ');
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sysControlDisplay(5,'4');
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sysControlDisplay(6,'5');
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sysControlDisplay(7,' ');
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}
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/**************************************************************************
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*
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* sysControlDisplay - controls one of the Alphanum. Display digits.
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*
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* This routine will write an ASCII character to the display digit requested.
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*
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* SEE ALSO:
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*
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* RETURNS: NA
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*/
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int sysControlDisplay (int digit, /* number of digit 0..7 */
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uchar ascii_code /* ASCII code */
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)
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{
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if ((digit < 0) || (digit > 7))
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return (-1);
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*((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;
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return (0);
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}
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#if defined(CONFIG_CMD_PCMCIA)
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#ifdef CFG_PCMCIA_MEM_ADDR
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volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
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#endif
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int pcmcia_init(void)
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{
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u_int rc;
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debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
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rc = i82365_init();
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return rc;
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}
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#endif
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# ifdef CONFIG_IDE_LED
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void ide_led (uchar led, uchar status)
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{
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u_char val;
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/* We have one PCMCIA slot and use LED H4 for the IDE Interface */
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val = readb(BCSR_BASE + 0x04);
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if (status) { /* led on */
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val |= B_CTRL_LED0;
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} else {
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val &= ~B_CTRL_LED0;
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}
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writeb(val, BCSR_BASE + 0x04);
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}
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# endif
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