upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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207 lines
5.9 KiB
207 lines
5.9 KiB
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/sdram.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/hmatrix.h>
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#include <lcd.h>
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#define SM_PM_GCCTRL 0x0060
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DECLARE_GLOBAL_DATA_PTR;
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static const struct sdram_config sdram_config = {
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.data_bits = SDRAM_DATA_16BIT,
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.row_bits = 13,
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.col_bits = 9,
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.bank_bits = 2,
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.cas = 3,
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.twr = 2,
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.trc = 6,
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.trp = 2,
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.trcd = 2,
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.tras = 6,
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.txsr = 6,
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/* 15.6 us */
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.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
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};
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int board_early_init_f(void)
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{
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/* Enable SDRAM in the EBI mux */
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hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
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gpio_enable_ebi();
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gpio_enable_usart1();
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/* enable higher address lines for larger flash devices */
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gpio_select_periph_A(GPIO_PIN_PE16, 0); /* ADDR23 */
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gpio_select_periph_A(GPIO_PIN_PE17, 0); /* ADDR24 */
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gpio_select_periph_A(GPIO_PIN_PE18, 0); /* ADDR25 */
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/* enable data flash chip select */
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gpio_select_periph_A(GPIO_PIN_PE25, 0); /* NCS2 */
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/* de-assert "force sys reset" pin */
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gpio_set_value(GPIO_PIN_PD15, 1); /* FORCE RESET */
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gpio_select_pio(GPIO_PIN_PD15, GPIOF_OUTPUT);
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/* init custom i/o */
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/* cpu type inputs */
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gpio_select_pio(GPIO_PIN_PE19, 0);
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gpio_select_pio(GPIO_PIN_PE20, 0);
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gpio_select_pio(GPIO_PIN_PE23, 0);
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/* main board type inputs */
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gpio_select_pio(GPIO_PIN_PB19, 0);
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gpio_select_pio(GPIO_PIN_PB29, 0);
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/* DEBUG input (use weak pullup) */
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gpio_select_pio(GPIO_PIN_PE21, GPIOF_PULLUP);
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/* are we suppressing the console ? */
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if (gpio_get_value(GPIO_PIN_PE21) == 1)
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gd->flags |= GD_FLG_SILENT;
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/* reset phys */
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gpio_select_pio(GPIO_PIN_PE24, 0);
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gpio_set_value(GPIO_PIN_PC18, 1); /* PHY RESET */
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gpio_select_pio(GPIO_PIN_PC18, GPIOF_OUTPUT);
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/* GCLK0 - 10MHz clock */
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writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL);
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gpio_select_periph_A(GPIO_PIN_PA30, 0);
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udelay(5000);
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/* release phys reset */
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gpio_set_value(GPIO_PIN_PC18, 0); /* PHY RESET (Release) */
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#if defined(CONFIG_MACB)
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/* init macb0 pins */
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gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
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gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */
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gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */
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gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */
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gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */
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gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */
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gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */
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gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */
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gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */
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gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */
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#if !defined(CONFIG_RMII)
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gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */
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gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */
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gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */
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gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */
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gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */
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gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */
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gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */
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gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */
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#endif
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/* init macb1 pins */
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gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */
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gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */
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gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */
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gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */
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gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */
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gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */
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gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */
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gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */
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gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */
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gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */
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#if !defined(CONFIG_RMII)
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gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */
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gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */
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gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */
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gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */
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gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */
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gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */
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gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */
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gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */
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#endif
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#endif
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#if defined(CONFIG_MMC)
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gpio_enable_mmci();
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#endif
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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unsigned long expected_size;
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unsigned long actual_size;
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void *sdram_base;
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sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
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expected_size = sdram_init(sdram_base, &sdram_config);
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actual_size = get_ram_size(sdram_base, expected_size);
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unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
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if (expected_size != actual_size)
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printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
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actual_size >> 20, expected_size >> 20);
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return actual_size;
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}
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void board_init_info(void)
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{
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gd->bd->bi_phy_id[0] = 0x01;
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gd->bd->bi_phy_id[1] = 0x03;
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}
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/* SPI chip select control */
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#ifdef CONFIG_ATMEL_SPI
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#include <spi.h>
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return (bus == 0) && (cs == 0);
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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}
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#endif /* CONFIG_ATMEL_SPI */
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#ifdef CONFIG_CMD_NET
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extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
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int board_eth_init(bd_t *bi)
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{
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macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
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macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
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return 0;
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}
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#endif
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