upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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54 lines
2.2 KiB
54 lines
2.2 KiB
/*
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
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*
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* u-boot/board/r7780mp/r7780mp.h
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _BOARD_R7780MP_R7780MP_H_
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#define _BOARD_R7780MP_R7780MP_H_
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/* R7780MP's FPGA register map */
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#define FPGA_BASE 0xa4000000
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#define FPGA_IRLMSK (FPGA_BASE + 0x00)
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#define FPGA_IRLMON (FPGA_BASE + 0x02)
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#define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
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#define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
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#define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
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#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
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#define FPGA_RSTCTL (FPGA_BASE + 0x0C)
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#define FPGA_PCIBD (FPGA_BASE + 0x0E)
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#define FPGA_PCICD (FPGA_BASE + 0x10)
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#define FPGA_EXTGIO (FPGA_BASE + 0x16)
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#define FPGA_IVDRMON (FPGA_BASE + 0x18)
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#define FPGA_IVDRCR (FPGA_BASE + 0x1A)
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#define FPGA_OBLED (FPGA_BASE + 0x1C)
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#define FPGA_OBSW (FPGA_BASE + 0x1E)
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#define FPGA_TPCTL (FPGA_BASE + 0x100)
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#define FPGA_TPDCKCTL (FPGA_BASE + 0x102)
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#define FPGA_TPCLR (FPGA_BASE + 0x104)
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#define FPGA_TPXPOS (FPGA_BASE + 0x106)
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#define FPGA_TPYPOS (FPGA_BASE + 0x108)
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#define FPGA_DBSW (FPGA_BASE + 0x200)
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#define FPGA_VERSION (FPGA_BASE + 0x700)
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#define FPGA_CFCTL (FPGA_BASE + 0x300)
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#define FPGA_CFPOW (FPGA_BASE + 0x302)
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#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304)
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#define FPGA_PMR (FPGA_BASE + 0x900)
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#endif /* _BOARD_R7780RP_R7780RP_H_ */
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