upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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269 lines
7.5 KiB
269 lines
7.5 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include "mpc8xx.h"
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#include <linux/mtd/doc2000.h>
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extern int kbd_init(void);
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extern int drv_kbd_init(void);
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] =
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{
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
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0x1FF77C47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x1FF7FC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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const uint static_table[] =
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{
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
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0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
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0xFFFFFC04, 0xFFFFFC05, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
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0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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* Test TQ ID string (TQM8xx...)
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* If present, check for "L" type (no second DRAM bank),
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* otherwise "L" type is assumed as default.
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*
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* Return 1 for "L" type, 0 else.
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*/
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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if (!s || strncmp (s, "TQM8", 4)) {
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printf ("### No HW ID - assuming RBC823\n");
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return (0);
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}
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puts (s);
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putc ('\n');
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size_b0, size8, size9;
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* 1 Bank of 64Mbit x 2 devices
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*/
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memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller SDRAM bank 0
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*/
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memctl->memc_or4 = CFG_OR4_PRELIM;
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memctl->memc_br4 = CFG_BR4_PRELIM;
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memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/*
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* Perform SDRAM initializsation sequence
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*/
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memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */
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udelay (1);
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memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
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udelay (200);
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memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */
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udelay (1);
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memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
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udelay (200);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /* 16: but should be: CFG_MPTPR_1BK_4K */
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
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SDRAM_MAX_SIZE);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
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SDRAM_MAX_SIZE);
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if (size8 < size9) { /* leave configuration at 9 columns */
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size_b0 = size9;
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/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
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} else { /* back to 8 columns */
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size_b0 = size8;
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memctl->memc_mamr = CFG_MAMR_8COL;
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udelay (500);
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/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
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}
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udelay (1000);
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/*
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* Adjust refresh rate depending on SDRAM type, both banks
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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if ((size_b0 < 0x02000000)) {
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
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udelay (1000);
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}
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/* SDRAM Bank 0 is bigger - map first */
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memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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udelay (10000);
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return (size_b0);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size (base, maxsize));
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}
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void doc_init (void)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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upmconfig (UPMB, (uint *) static_table,
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sizeof (static_table) / sizeof (uint));
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memctl->memc_mbmr = MAMR_DSA_1_CYCL;
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doc_probe (FLASH_BASE1_PRELIM);
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}
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