upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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294 lines
7.8 KiB
294 lines
7.8 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <commproc.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sharc_table[] = {
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/*
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* Single Read. (Offset 0 in UPM RAM)
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*/
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0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
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0xFFFFEC05, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Read. (Offset 8 in UPM RAM)
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*/
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/* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPM RAM)
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*/
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0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
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0xFFFFEC05, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPM RAM)
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*/
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/* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPM RAM)
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*/
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/* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPM RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPM RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
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0x1FF77C47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPM RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPM RAM)
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*/
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0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPM RAM)
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*/
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0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPM RAM)
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*/
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0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPM RAM)
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*/
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0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPM RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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*/
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int checkboard (void)
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{
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puts ("Board: SPD823TS\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size_b0;
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#if 0
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/*
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* Map controller bank 2 to the SRAM bank at preliminary address.
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*/
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memctl->memc_or2 = CFG_OR2;
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memctl->memc_br2 = CFG_BR2;
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#endif
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/*
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* Map controller bank 4 to the PER8 bank.
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*/
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memctl->memc_or4 = CFG_OR4;
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memctl->memc_br4 = CFG_BR4;
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#if 0
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/* Configure SHARC at UMA */
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upmconfig (UPMA, (uint *) sharc_table,
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sizeof (sharc_table) / sizeof (uint));
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/* Map controller bank 5 to the SHARC */
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memctl->memc_or5 = CFG_OR5;
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memctl->memc_br5 = CFG_BR5;
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#endif
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memctl->memc_mamr = 0x00001000;
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/* Configure SDRAM at UMB */
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upmconfig (UPMB, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller bank 3 to the SDRAM bank at preliminary address.
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*/
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memctl->memc_or3 = CFG_OR3_PRELIM;
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memctl->memc_br3 = CFG_BR3_PRELIM;
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memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
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udelay (200);
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memctl->memc_mcr = 0x80806105;
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udelay (1);
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memctl->memc_mcr = 0x80806130;
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udelay (1);
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memctl->memc_mcr = 0x80806130;
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udelay (1);
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memctl->memc_mcr = 0x80806106;
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memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
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/*
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* Check Bank 0 Memory Size for re-configuration
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*/
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size_b0 =
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dram_size (CFG_MBMR_8COL, SDRAM_BASE3_PRELIM,
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SDRAM_MAX_SIZE);
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memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
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return (size_b0);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mbmr = mamr_value;
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return (get_ram_size (base, maxsize));
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}
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/* ------------------------------------------------------------------------- */
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void reset_phy (void)
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{
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immap_t *immr = (immap_t *) CFG_IMMR;
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ushort sreg;
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/* Configure extra port pins for NS DP83843 PHY */
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immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO);
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sreg = immr->im_ioport.iop_padir;
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sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */
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sreg &= ~(PA_ENET_MDIO); /* Mgmt. Data I/O is bidirect. => Input */
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immr->im_ioport.iop_padir = sreg;
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immr->im_ioport.iop_padat &= ~(PA_ENET_MDC); /* set MDC = 0 */
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/*
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* RESET in implemented by a positive pulse of at least 1 us
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* at the reset pin.
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*
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* Configure RESET pins for NS DP83843 PHY, and RESET chip.
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*
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* Note: The RESET pin is high active, but there is an
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* inverter on the SPD823TS board...
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*/
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immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET);
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immr->im_ioport.iop_pcdir |= PC_ENET_RESET;
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/* assert RESET signal of PHY */
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immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET);
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udelay (10);
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/* de-assert RESET signal of PHY */
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immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
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udelay (10);
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}
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/* ------------------------------------------------------------------------- */
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void ide_set_reset (int on)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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/*
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* Configure PC for IDE Reset Pin
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*/
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if (on) { /* assert RESET */
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immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
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} else { /* release RESET */
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immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
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}
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/* program port pin as GPIO output */
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immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
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immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
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immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
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}
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/* ------------------------------------------------------------------------- */
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