upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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764 lines
19 KiB
764 lines
19 KiB
/*
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dm9000.c: Version 1.2 12/15/2003
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A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
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Copyright (C) 1997 Sten Wang
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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(C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
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V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
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06/22/2001 Support DM9801 progrmming
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E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
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E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
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R17 = (R17 & 0xfff0) | NF + 3
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E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
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R17 = (R17 & 0xfff0) | NF
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v1.00 modify by simon 2001.9.5
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change for kernel 2.4.x
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v1.1 11/09/2001 fix force mode bug
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v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
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Fixed phy reset.
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Added tx/rx 32 bit mode.
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Cleaned up for kernel merge.
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--------------------------------------
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12/15/2003 Initial port to u-boot by
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Sascha Hauer <saschahauer@web.de>
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06/03/2008 Remy Bohmer <linux@bohmer.net>
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- Fixed the driver to work with DM9000A.
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(check on ISR receive status bit before reading the
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FIFO as described in DM9000 programming guide and
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application notes)
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- Added autodetect of databus width.
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- Made debug code compile again.
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- Adapt eth_send such that it matches the DM9000*
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application notes. Needed to make it work properly
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for DM9000A.
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- Adapted reset procedure to match DM9000 application
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notes (i.e. double reset)
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- some minor code cleanups
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These changes are tested with DM9000{A,EP,E} together
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with a 200MHz Atmel AT91SAM92161 core
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TODO: Homerun NIC and longrun NIC are not functional, only internal at the
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moment.
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*/
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#include <common.h>
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#include <command.h>
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#include <net.h>
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#include <asm/io.h>
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#include "dm9000x.h"
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/* Board/System/Debug information/definition ---------------- */
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#define DM9801_NOISE_FLOOR 0x08
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#define DM9802_NOISE_FLOOR 0x05
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/* #define CONFIG_DM9000_DEBUG */
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#ifdef CONFIG_DM9000_DEBUG
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#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
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#define DM9000_DMP_PACKET(func,packet,length) \
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do { \
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int i; \
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printf(func ": length: %d\n", length); \
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for (i = 0; i < length; i++) { \
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if (i % 8 == 0) \
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printf("\n%s: %02x: ", func, i); \
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printf("%02x ", ((unsigned char *) packet)[i]); \
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} printf("\n"); \
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} while(0)
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#else
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#define DM9000_DBG(fmt,args...)
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#define DM9000_DMP_PACKET(func,packet,length)
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#endif
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enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD =
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1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO =
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8, DM9000_1M_HPNA = 0x10
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};
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enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2
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};
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/* Structure/enum declaration ------------------------------- */
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typedef struct board_info {
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u32 runt_length_counter; /* counter: RX length < 64byte */
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u32 long_length_counter; /* counter: RX length > 1514byte */
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u32 reset_counter; /* counter: RESET */
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u32 reset_tx_timeout; /* RESET caused by TX Timeout */
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u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
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u16 tx_pkt_cnt;
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u16 queue_start_addr;
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u16 dbug_cnt;
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u8 phy_addr;
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u8 device_wait_reset; /* device state */
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u8 nic_type; /* NIC type */
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unsigned char srom[128];
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void (*outblk)(volatile void *data_ptr, int count);
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void (*inblk)(void *data_ptr, int count);
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void (*rx_status)(u16 *RxStatus, u16 *RxLen);
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} board_info_t;
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static board_info_t dm9000_info;
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/* For module input parameter */
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static int media_mode = DM9000_AUTO;
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static u8 nfloor = 0;
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/* function declaration ------------------------------------- */
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int eth_init(bd_t * bd);
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int eth_send(volatile void *, int);
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int eth_rx(void);
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void eth_halt(void);
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static int dm9000_probe(void);
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static u16 phy_read(int);
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static void phy_write(int, u16);
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u16 read_srom_word(int);
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static u8 DM9000_ior(int);
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static void DM9000_iow(int reg, u8 value);
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/* DM9000 network board routine ---------------------------- */
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#define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
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#define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
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#define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
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#define DM9000_inb(r) (*(volatile u8 *)r)
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#define DM9000_inw(r) (*(volatile u16 *)r)
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#define DM9000_inl(r) (*(volatile u32 *)r)
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#ifdef CONFIG_DM9000_DEBUG
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static void
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dump_regs(void)
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{
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DM9000_DBG("\n");
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DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
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DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
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DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
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DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
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DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
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DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
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DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
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DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
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DM9000_DBG("\n");
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}
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#endif
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static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
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{
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int i;
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for (i = 0; i < count; i++)
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DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
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}
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static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
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{
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int i;
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u32 tmplen = (count + 1) / 2;
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for (i = 0; i < tmplen; i++)
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DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
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}
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static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
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{
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int i;
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u32 tmplen = (count + 3) / 4;
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for (i = 0; i < tmplen; i++)
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DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
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}
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static void dm9000_inblk_8bit(void *data_ptr, int count)
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{
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int i;
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for (i = 0; i < count; i++)
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((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
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}
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static void dm9000_inblk_16bit(void *data_ptr, int count)
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{
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int i;
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u32 tmplen = (count + 1) / 2;
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for (i = 0; i < tmplen; i++)
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((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
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}
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static void dm9000_inblk_32bit(void *data_ptr, int count)
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{
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int i;
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u32 tmplen = (count + 3) / 4;
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for (i = 0; i < tmplen; i++)
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((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
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}
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static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
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{
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u32 tmpdata;
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DM9000_outb(DM9000_MRCMD, DM9000_IO);
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tmpdata = DM9000_inl(DM9000_DATA);
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*RxStatus = __le16_to_cpu(tmpdata);
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*RxLen = __le16_to_cpu(tmpdata >> 16);
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}
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static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
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{
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DM9000_outb(DM9000_MRCMD, DM9000_IO);
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*RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
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*RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
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}
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static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
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{
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DM9000_outb(DM9000_MRCMD, DM9000_IO);
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*RxStatus =
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__le16_to_cpu(DM9000_inb(DM9000_DATA) +
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(DM9000_inb(DM9000_DATA) << 8));
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*RxLen =
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__le16_to_cpu(DM9000_inb(DM9000_DATA) +
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(DM9000_inb(DM9000_DATA) << 8));
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}
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/*
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Search DM9000 board, allocate space and register it
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*/
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int
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dm9000_probe(void)
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{
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u32 id_val;
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id_val = DM9000_ior(DM9000_VIDL);
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id_val |= DM9000_ior(DM9000_VIDH) << 8;
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id_val |= DM9000_ior(DM9000_PIDL) << 16;
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id_val |= DM9000_ior(DM9000_PIDH) << 24;
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if (id_val == DM9000_ID) {
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printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
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id_val);
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return 0;
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} else {
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printf("dm9000 not found at 0x%08x id: 0x%08x\n",
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CONFIG_DM9000_BASE, id_val);
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return -1;
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}
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}
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/* Set PHY operationg mode
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*/
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static void
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set_PHY_mode(void)
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{
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u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
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if (!(media_mode & DM9000_AUTO)) {
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switch (media_mode) {
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case DM9000_10MHD:
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phy_reg4 = 0x21;
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phy_reg0 = 0x0000;
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break;
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case DM9000_10MFD:
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phy_reg4 = 0x41;
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phy_reg0 = 0x1100;
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break;
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case DM9000_100MHD:
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phy_reg4 = 0x81;
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phy_reg0 = 0x2000;
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break;
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case DM9000_100MFD:
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phy_reg4 = 0x101;
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phy_reg0 = 0x3100;
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break;
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}
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phy_write(4, phy_reg4); /* Set PHY media mode */
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phy_write(0, phy_reg0); /* Tmp */
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}
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DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */
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DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */
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}
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/*
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Init HomeRun DM9801
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*/
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static void
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program_dm9801(u16 HPNA_rev)
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{
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__u16 reg16, reg17, reg24, reg25;
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if (!nfloor)
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nfloor = DM9801_NOISE_FLOOR;
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reg16 = phy_read(16);
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reg17 = phy_read(17);
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reg24 = phy_read(24);
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reg25 = phy_read(25);
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switch (HPNA_rev) {
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case 0xb900: /* DM9801 E3 */
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reg16 |= 0x1000;
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reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000;
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break;
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case 0xb901: /* DM9801 E4 */
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reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200;
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reg17 = (reg17 & 0xfff0) + nfloor + 3;
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break;
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case 0xb902: /* DM9801 E5 */
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case 0xb903: /* DM9801 E6 */
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default:
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reg16 |= 0x1000;
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reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200;
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reg17 = (reg17 & 0xfff0) + nfloor;
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}
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phy_write(16, reg16);
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phy_write(17, reg17);
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phy_write(25, reg25);
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}
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/*
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Init LongRun DM9802
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*/
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static void
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program_dm9802(void)
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{
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__u16 reg25;
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if (!nfloor)
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nfloor = DM9802_NOISE_FLOOR;
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reg25 = phy_read(25);
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reg25 = (reg25 & 0xff00) + nfloor;
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phy_write(25, reg25);
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}
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/* Identify NIC type
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*/
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static void
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identify_nic(void)
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{
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struct board_info *db = &dm9000_info;
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u16 phy_reg3;
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DM9000_iow(DM9000_NCR, NCR_EXT_PHY);
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phy_reg3 = phy_read(3);
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switch (phy_reg3 & 0xfff0) {
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case 0xb900:
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if (phy_read(31) == 0x4404) {
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db->nic_type = HOMERUN_NIC;
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program_dm9801(phy_reg3);
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DM9000_DBG("found homerun NIC\n");
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} else {
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db->nic_type = LONGRUN_NIC;
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DM9000_DBG("found longrun NIC\n");
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program_dm9802();
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}
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break;
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default:
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db->nic_type = FASTETHER_NIC;
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break;
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}
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DM9000_iow(DM9000_NCR, 0);
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}
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/* General Purpose dm9000 reset routine */
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static void
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dm9000_reset(void)
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{
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DM9000_DBG("resetting DM9000\n");
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/* Reset DM9000,
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see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
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/* DEBUG: Make all GPIO pins outputs */
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DM9000_iow(DM9000_GPCR, 0x0F);
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/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
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DM9000_iow(DM9000_GPR, 0);
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/* Step 2: Software reset */
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DM9000_iow(DM9000_NCR, 3);
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do {
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DM9000_DBG("resetting the DM9000, 1st reset\n");
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udelay(25); /* Wait at least 20 us */
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} while (DM9000_ior(DM9000_NCR) & 1);
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DM9000_iow(DM9000_NCR, 0);
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DM9000_iow(DM9000_NCR, 3); /* Issue a second reset */
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do {
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DM9000_DBG("resetting the DM9000, 2nd reset\n");
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udelay(25); /* Wait at least 20 us */
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} while (DM9000_ior(DM9000_NCR) & 1);
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|
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/* Check whether the ethernet controller is present */
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if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
|
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(DM9000_ior(DM9000_PIDH) != 0x90))
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printf("ERROR: resetting DM9000 -> not responding\n");
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}
|
|
|
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/* Initilize dm9000 board
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*/
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int
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eth_init(bd_t * bd)
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{
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int i, oft, lnk;
|
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u8 io_mode;
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struct board_info *db = &dm9000_info;
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|
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DM9000_DBG("eth_init()\n");
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|
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/* RESET device */
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dm9000_reset();
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dm9000_probe();
|
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|
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/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
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io_mode = DM9000_ior(DM9000_ISR) >> 6;
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|
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switch (io_mode) {
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case 0x0: /* 16-bit mode */
|
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printf("DM9000: running in 16 bit mode\n");
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db->outblk = dm9000_outblk_16bit;
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db->inblk = dm9000_inblk_16bit;
|
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db->rx_status = dm9000_rx_status_16bit;
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break;
|
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case 0x01: /* 32-bit mode */
|
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printf("DM9000: running in 32 bit mode\n");
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db->outblk = dm9000_outblk_32bit;
|
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db->inblk = dm9000_inblk_32bit;
|
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db->rx_status = dm9000_rx_status_32bit;
|
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break;
|
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case 0x02: /* 8 bit mode */
|
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printf("DM9000: running in 8 bit mode\n");
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db->outblk = dm9000_outblk_8bit;
|
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db->inblk = dm9000_inblk_8bit;
|
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db->rx_status = dm9000_rx_status_8bit;
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break;
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default:
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/* Assume 8 bit mode, will probably not work anyway */
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printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
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db->outblk = dm9000_outblk_8bit;
|
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db->inblk = dm9000_inblk_8bit;
|
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db->rx_status = dm9000_rx_status_8bit;
|
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break;
|
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}
|
|
|
|
/* NIC Type: FASTETHER, HOMERUN, LONGRUN */
|
|
identify_nic();
|
|
|
|
/* GPIO0 on pre-activate PHY */
|
|
DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
|
|
|
|
/* Set PHY */
|
|
set_PHY_mode();
|
|
|
|
/* Program operating register, only intern phy supported by now */
|
|
DM9000_iow(DM9000_NCR, 0x0);
|
|
/* TX Polling clear */
|
|
DM9000_iow(DM9000_TCR, 0);
|
|
/* Less 3Kb, 200us */
|
|
DM9000_iow(DM9000_BPTR, 0x3f);
|
|
/* Flow Control : High/Low Water */
|
|
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
|
|
/* SH FIXME: This looks strange! Flow Control */
|
|
DM9000_iow(DM9000_FCR, 0x0);
|
|
/* Special Mode */
|
|
DM9000_iow(DM9000_SMCR, 0);
|
|
/* clear TX status */
|
|
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
|
|
/* Clear interrupt status */
|
|
DM9000_iow(DM9000_ISR, 0x0f);
|
|
|
|
/* Set Node address */
|
|
#ifndef CONFIG_AT91SAM9261EK
|
|
for (i = 0; i < 6; i++)
|
|
((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
|
|
#endif
|
|
|
|
if (is_zero_ether_addr(bd->bi_enetaddr) ||
|
|
is_multicast_ether_addr(bd->bi_enetaddr)) {
|
|
/* try reading from environment */
|
|
u8 i;
|
|
char *s, *e;
|
|
s = getenv ("ethaddr");
|
|
for (i = 0; i < 6; ++i) {
|
|
bd->bi_enetaddr[i] = s ?
|
|
simple_strtoul (s, &e, 16) : 0;
|
|
if (s)
|
|
s = (*e) ? e + 1 : e;
|
|
}
|
|
}
|
|
|
|
printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
|
|
bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
|
|
bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
|
|
for (i = 0, oft = 0x10; i < 6; i++, oft++)
|
|
DM9000_iow(oft, bd->bi_enetaddr[i]);
|
|
for (i = 0, oft = 0x16; i < 8; i++, oft++)
|
|
DM9000_iow(oft, 0xff);
|
|
|
|
/* read back mac, just to be sure */
|
|
for (i = 0, oft = 0x10; i < 6; i++, oft++)
|
|
DM9000_DBG("%02x:", DM9000_ior(oft));
|
|
DM9000_DBG("\n");
|
|
|
|
/* Activate DM9000 */
|
|
/* RX enable */
|
|
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
|
|
/* Enable TX/RX interrupt mask */
|
|
DM9000_iow(DM9000_IMR, IMR_PAR);
|
|
|
|
i = 0;
|
|
while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
|
|
udelay(1000);
|
|
i++;
|
|
if (i == 10000) {
|
|
printf("could not establish link\n");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* see what we've got */
|
|
lnk = phy_read(17) >> 12;
|
|
printf("operating at ");
|
|
switch (lnk) {
|
|
case 1:
|
|
printf("10M half duplex ");
|
|
break;
|
|
case 2:
|
|
printf("10M full duplex ");
|
|
break;
|
|
case 4:
|
|
printf("100M half duplex ");
|
|
break;
|
|
case 8:
|
|
printf("100M full duplex ");
|
|
break;
|
|
default:
|
|
printf("unknown: %d ", lnk);
|
|
break;
|
|
}
|
|
printf("mode\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
Hardware start transmission.
|
|
Send a packet to media from the upper layer.
|
|
*/
|
|
int
|
|
eth_send(volatile void *packet, int length)
|
|
{
|
|
int tmo;
|
|
struct board_info *db = &dm9000_info;
|
|
|
|
DM9000_DMP_PACKET("eth_send", packet, length);
|
|
|
|
DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
|
|
|
|
/* Move data to DM9000 TX RAM */
|
|
DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
|
|
|
|
/* push the data to the TX-fifo */
|
|
(db->outblk)(packet, length);
|
|
|
|
/* Set TX length to DM9000 */
|
|
DM9000_iow(DM9000_TXPLL, length & 0xff);
|
|
DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
|
|
|
|
/* Issue TX polling command */
|
|
DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
|
|
|
|
/* wait for end of transmission */
|
|
tmo = get_timer(0) + 5 * CFG_HZ;
|
|
while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
|
|
!(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
|
|
if (get_timer(0) >= tmo) {
|
|
printf("transmission timeout\n");
|
|
break;
|
|
}
|
|
}
|
|
DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
|
|
|
|
DM9000_DBG("transmit done\n\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
Stop the interface.
|
|
The interface is stopped when it is brought.
|
|
*/
|
|
void
|
|
eth_halt(void)
|
|
{
|
|
DM9000_DBG("eth_halt\n");
|
|
|
|
/* RESET devie */
|
|
phy_write(0, 0x8000); /* PHY RESET */
|
|
DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
|
|
DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
|
|
DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
|
|
}
|
|
|
|
/*
|
|
Received a packet and pass to upper layer
|
|
*/
|
|
int
|
|
eth_rx(void)
|
|
{
|
|
u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
|
|
u16 RxStatus, RxLen = 0;
|
|
struct board_info *db = &dm9000_info;
|
|
|
|
/* Check packet ready or not, we must check
|
|
the ISR status first for DM9000A */
|
|
if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
|
|
return 0;
|
|
|
|
DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
|
|
|
|
/* There is _at least_ 1 package in the fifo, read them all */
|
|
for (;;) {
|
|
DM9000_ior(DM9000_MRCMDX); /* Dummy read */
|
|
|
|
/* Get most updated data,
|
|
only look at bits 0:1, See application notes DM9000 */
|
|
rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
|
|
|
|
/* Status check: this byte must be 0 or 1 */
|
|
if (rxbyte > DM9000_PKT_RDY) {
|
|
DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
|
|
DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
|
|
printf("DM9000 error: status check fail: 0x%x\n",
|
|
rxbyte);
|
|
return 0;
|
|
}
|
|
|
|
if (rxbyte != DM9000_PKT_RDY)
|
|
return 0; /* No packet received, ignore */
|
|
|
|
DM9000_DBG("receiving packet\n");
|
|
|
|
/* A packet ready now & Get status/length */
|
|
(db->rx_status)(&RxStatus, &RxLen);
|
|
|
|
DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
|
|
|
|
/* Move data from DM9000 */
|
|
/* Read received packet from RX SRAM */
|
|
(db->inblk)(rdptr, RxLen);
|
|
|
|
if ((RxStatus & 0xbf00) || (RxLen < 0x40)
|
|
|| (RxLen > DM9000_PKT_MAX)) {
|
|
if (RxStatus & 0x100) {
|
|
printf("rx fifo error\n");
|
|
}
|
|
if (RxStatus & 0x200) {
|
|
printf("rx crc error\n");
|
|
}
|
|
if (RxStatus & 0x8000) {
|
|
printf("rx length error\n");
|
|
}
|
|
if (RxLen > DM9000_PKT_MAX) {
|
|
printf("rx length too big\n");
|
|
dm9000_reset();
|
|
}
|
|
} else {
|
|
DM9000_DMP_PACKET("eth_rx", rdptr, RxLen);
|
|
|
|
DM9000_DBG("passing packet to upper layer\n");
|
|
NetReceive(NetRxPackets[0], RxLen);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
Read a word data from SROM
|
|
*/
|
|
u16
|
|
read_srom_word(int offset)
|
|
{
|
|
DM9000_iow(DM9000_EPAR, offset);
|
|
DM9000_iow(DM9000_EPCR, 0x4);
|
|
udelay(8000);
|
|
DM9000_iow(DM9000_EPCR, 0x0);
|
|
return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
|
|
}
|
|
|
|
void
|
|
write_srom_word(int offset, u16 val)
|
|
{
|
|
DM9000_iow(DM9000_EPAR, offset);
|
|
DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
|
|
DM9000_iow(DM9000_EPDRL, (val & 0xff));
|
|
DM9000_iow(DM9000_EPCR, 0x12);
|
|
udelay(8000);
|
|
DM9000_iow(DM9000_EPCR, 0);
|
|
}
|
|
|
|
|
|
/*
|
|
Read a byte from I/O port
|
|
*/
|
|
static u8
|
|
DM9000_ior(int reg)
|
|
{
|
|
DM9000_outb(reg, DM9000_IO);
|
|
return DM9000_inb(DM9000_DATA);
|
|
}
|
|
|
|
/*
|
|
Write a byte to I/O port
|
|
*/
|
|
static void
|
|
DM9000_iow(int reg, u8 value)
|
|
{
|
|
DM9000_outb(reg, DM9000_IO);
|
|
DM9000_outb(value, DM9000_DATA);
|
|
}
|
|
|
|
/*
|
|
Read a word from phyxcer
|
|
*/
|
|
static u16
|
|
phy_read(int reg)
|
|
{
|
|
u16 val;
|
|
|
|
/* Fill the phyxcer register into REG_0C */
|
|
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
|
|
DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
|
|
udelay(100); /* Wait read complete */
|
|
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
|
|
val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
|
|
|
|
/* The read data keeps on REG_0D & REG_0E */
|
|
DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val);
|
|
return val;
|
|
}
|
|
|
|
/*
|
|
Write a word to phyxcer
|
|
*/
|
|
static void
|
|
phy_write(int reg, u16 value)
|
|
{
|
|
|
|
/* Fill the phyxcer register into REG_0C */
|
|
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
|
|
|
|
/* Fill the written data into REG_0D & REG_0E */
|
|
DM9000_iow(DM9000_EPDRL, (value & 0xff));
|
|
DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
|
|
DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
|
|
udelay(500); /* Wait write complete */
|
|
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
|
|
DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
|
|
}
|
|
|