upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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116 lines
3.4 KiB
116 lines
3.4 KiB
/*
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* include/asm-microblaze/ptrace.h -- Access to CPU registers
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*
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* Copyright (C) 2003 John Williams <jwilliams@itee.uq.edu.au>
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* Copyright (C) 2001,2002 NEC Corporation
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* Copyright (C) 2001,2002 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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* Microblaze port by John Williams
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*/
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#ifndef __MICROBLAZE_PTRACE_H__
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#define __MICROBLAZE_PTRACE_H__
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/* Microblaze general purpose registers with special meanings. */
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#define GPR_ZERO 0 /* constant zero */
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#define GPR_ASM 18 /* reserved for assembler */
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#define GPR_SP 1 /* stack pointer */
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#define GPR_GP 2 /* global data pointer */
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#define GPR_EP 30 /* `element pointer' */
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#define GPR_LP 15 /* link pointer (current return address) */
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/* These aren't official names, but they make some code more descriptive. */
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#define GPR_ARG0 5
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#define GPR_ARG1 6
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#define GPR_ARG2 7
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#define GPR_ARG3 8
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#define GPR_ARG4 9
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#define GPR_ARG5 10
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#define GPR_RVAL0 3
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#define GPR_RVAL1 4
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#define GPR_RVAL GPR_RVAL0
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#define NUM_GPRS 32
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/* `system' registers. */
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/* Note these are old v850 values, microblaze has many fewer */
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#define SR_EIPC 0
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#define SR_EIPSW 1
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#define SR_FEPC 2
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#define SR_FEPSW 3
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#define SR_ECR 4
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#define SR_PSW 5
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#define SR_CTPC 16
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#define SR_CTPSW 17
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#define SR_DBPC 18
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#define SR_DBPSW 19
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#define SR_CTBP 20
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#define SR_DIR 21
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#define SR_ASID 23
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#ifndef __ASSEMBLY__
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typedef unsigned long microblaze_reg_t;
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/* How processor state is stored on the stack during a syscall/signal.
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If you change this structure, change the associated assembly-language
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macros below too (PT_*)! */
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struct pt_regs
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{
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/* General purpose registers. */
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microblaze_reg_t gpr[NUM_GPRS];
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microblaze_reg_t pc; /* program counter */
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microblaze_reg_t psw; /* program status word */
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microblaze_reg_t kernel_mode; /* 1 if in `kernel mode', 0 if user mode */
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microblaze_reg_t single_step; /* 1 if in single step mode */
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};
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#define instruction_pointer(regs) ((regs)->pc)
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#define user_mode(regs) (!(regs)->kernel_mode)
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/* When a struct pt_regs is used to save user state for a system call in
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the kernel, the system call is stored in the space for R0 (since it's
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never used otherwise, R0 being a constant 0). Non-system-calls
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simply store 0 there. */
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#define PT_REGS_SYSCALL(regs) (regs)->gpr[0]
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#define PT_REGS_SET_SYSCALL(regs, val) ((regs)->gpr[0] = (val))
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#endif /* !__ASSEMBLY__ */
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/* The number of bytes used to store each register. */
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#define _PT_REG_SIZE 4
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/* Offset of a general purpose register in a stuct pt_regs. */
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#define PT_GPR(num) ((num) * _PT_REG_SIZE)
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/* Offsets of various special registers & fields in a struct pt_regs. */
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#define NUM_SPECIAL 4
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#define PT_PC ((NUM_GPRS + 0) * _PT_REG_SIZE)
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#define PT_PSW ((NUM_GPRS + 1) * _PT_REG_SIZE)
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#define PT_KERNEL_MODE ((NUM_GPRS + 2) * _PT_REG_SIZE)
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#define PT_SINGLESTEP ((NUM_GPRS + 3) * _PT_REG_SIZE)
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#define PT_SYSCALL PT_GPR(0)
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/* Size of struct pt_regs, including alignment. */
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#define PT_SIZE ((NUM_GPRS + NUM_SPECIAL) * _PT_REG_SIZE)
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/* These are `magic' values for PTRACE_PEEKUSR that return info about where
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a process is located in memory. */
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#define PT_TEXT_ADDR (PT_SIZE + 1)
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#define PT_TEXT_LEN (PT_SIZE + 2)
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#define PT_DATA_ADDR (PT_SIZE + 3)
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#define PT_DATA_LEN (PT_SIZE + 4)
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#endif /* __MICROBLAZE_PTRACE_H__ */
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