upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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54 lines
1.0 KiB
54 lines
1.0 KiB
/*
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* (C) Copyright 2010 Linaro
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* Matt Waddel, <matt.waddel@linaro.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SYSCTRL_H_
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#define _SYSCTRL_H_
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/* System controller (SP810) register definitions */
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#define SP810_TIMER0_ENSEL (1 << 15)
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#define SP810_TIMER1_ENSEL (1 << 17)
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#define SP810_TIMER2_ENSEL (1 << 19)
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#define SP810_TIMER3_ENSEL (1 << 21)
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struct sysctrl {
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u32 scctrl; /* 0x000 */
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u32 scsysstat;
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u32 scimctrl;
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u32 scimstat;
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u32 scxtalctrl;
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u32 scpllctrl;
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u32 scpllfctrl;
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u32 scperctrl0;
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u32 scperctrl1;
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u32 scperen;
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u32 scperdis;
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u32 scperclken;
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u32 scperstat;
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u32 res1[0x006];
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u32 scflashctrl; /* 0x04c */
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u32 res2[0x3a4];
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u32 scsysid0; /* 0xee0 */
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u32 scsysid1;
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u32 scsysid2;
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u32 scsysid3;
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u32 scitcr;
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u32 scitir0;
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u32 scitir1;
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u32 scitor;
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u32 sccntctrl;
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u32 sccntdata;
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u32 sccntstep;
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u32 res3[0x32];
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u32 scperiphid0; /* 0xfe0 */
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u32 scperiphid1;
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u32 scperiphid2;
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u32 scperiphid3;
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u32 scpcellid0;
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u32 scpcellid1;
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u32 scpcellid2;
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u32 scpcellid3;
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};
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#endif /* _SYSCTRL_H_ */
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