upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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50 lines
1.1 KiB
50 lines
1.1 KiB
/*
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* (C) Copyright 2009
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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#include <asm/imx-common/regs-common.h>
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#define MXC_CPU_MX51 0x51
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#define MXC_CPU_MX53 0x53
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#define MXC_CPU_MX6SL 0x60
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#define MXC_CPU_MX6DL 0x61
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#define MXC_CPU_MX6SOLO 0x62
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#define MXC_CPU_MX6Q 0x63
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#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
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u32 get_cpu_rev(void);
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/* returns MXC_CPU_ value */
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#define cpu_type(rev) (((rev) >> 12)&0xff)
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/* use with MXC_CPU_ constants */
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#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
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const char *get_imx_type(u32 imxtype);
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unsigned imx_ddr_size(void);
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void set_vddsoc(u32 mv);
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int fecmxc_initialize(bd_t *bis);
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u32 get_ahb_clk(void);
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u32 get_periph_clk(void);
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int mxs_reset_block(struct mxs_register_32 *reg);
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int mxs_wait_mask_set(struct mxs_register_32 *reg,
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uint32_t mask,
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unsigned int timeout);
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int mxs_wait_mask_clr(struct mxs_register_32 *reg,
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uint32_t mask,
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unsigned int timeout);
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#endif
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