upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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163 lines
4.1 KiB
163 lines
4.1 KiB
/*
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* (C) Copyright 2009 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_GPIO_H
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#define __ASM_ARCH_GPIO_H
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#ifndef __ASSEMBLY__
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struct s5p_gpio_bank {
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unsigned int con;
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unsigned int dat;
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unsigned int pull;
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unsigned int drv;
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unsigned int pdn_con;
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unsigned int pdn_pull;
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unsigned char res1[8];
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};
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struct s5pc100_gpio {
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struct s5p_gpio_bank a0;
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struct s5p_gpio_bank a1;
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struct s5p_gpio_bank b;
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struct s5p_gpio_bank c;
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struct s5p_gpio_bank d;
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struct s5p_gpio_bank e0;
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struct s5p_gpio_bank e1;
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struct s5p_gpio_bank f0;
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struct s5p_gpio_bank f1;
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struct s5p_gpio_bank f2;
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struct s5p_gpio_bank f3;
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struct s5p_gpio_bank g0;
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struct s5p_gpio_bank g1;
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struct s5p_gpio_bank g2;
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struct s5p_gpio_bank g3;
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struct s5p_gpio_bank i;
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struct s5p_gpio_bank j0;
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struct s5p_gpio_bank j1;
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struct s5p_gpio_bank j2;
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struct s5p_gpio_bank j3;
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struct s5p_gpio_bank j4;
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struct s5p_gpio_bank k0;
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struct s5p_gpio_bank k1;
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struct s5p_gpio_bank k2;
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struct s5p_gpio_bank k3;
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struct s5p_gpio_bank l0;
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struct s5p_gpio_bank l1;
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struct s5p_gpio_bank l2;
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struct s5p_gpio_bank l3;
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struct s5p_gpio_bank l4;
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struct s5p_gpio_bank h0;
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struct s5p_gpio_bank h1;
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struct s5p_gpio_bank h2;
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struct s5p_gpio_bank h3;
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};
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struct s5pc110_gpio {
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struct s5p_gpio_bank a0;
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struct s5p_gpio_bank a1;
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struct s5p_gpio_bank b;
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struct s5p_gpio_bank c0;
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struct s5p_gpio_bank c1;
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struct s5p_gpio_bank d0;
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struct s5p_gpio_bank d1;
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struct s5p_gpio_bank e0;
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struct s5p_gpio_bank e1;
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struct s5p_gpio_bank f0;
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struct s5p_gpio_bank f1;
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struct s5p_gpio_bank f2;
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struct s5p_gpio_bank f3;
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struct s5p_gpio_bank g0;
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struct s5p_gpio_bank g1;
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struct s5p_gpio_bank g2;
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struct s5p_gpio_bank g3;
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struct s5p_gpio_bank i;
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struct s5p_gpio_bank j0;
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struct s5p_gpio_bank j1;
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struct s5p_gpio_bank j2;
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struct s5p_gpio_bank j3;
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struct s5p_gpio_bank j4;
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struct s5p_gpio_bank mp0_1;
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struct s5p_gpio_bank mp0_2;
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struct s5p_gpio_bank mp0_3;
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struct s5p_gpio_bank mp0_4;
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struct s5p_gpio_bank mp0_5;
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struct s5p_gpio_bank mp0_6;
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struct s5p_gpio_bank mp0_7;
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struct s5p_gpio_bank mp1_0;
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struct s5p_gpio_bank mp1_1;
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struct s5p_gpio_bank mp1_2;
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struct s5p_gpio_bank mp1_3;
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struct s5p_gpio_bank mp1_4;
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struct s5p_gpio_bank mp1_5;
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struct s5p_gpio_bank mp1_6;
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struct s5p_gpio_bank mp1_7;
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struct s5p_gpio_bank mp1_8;
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struct s5p_gpio_bank mp2_0;
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struct s5p_gpio_bank mp2_1;
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struct s5p_gpio_bank mp2_2;
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struct s5p_gpio_bank mp2_3;
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struct s5p_gpio_bank mp2_4;
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struct s5p_gpio_bank mp2_5;
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struct s5p_gpio_bank mp2_6;
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struct s5p_gpio_bank mp2_7;
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struct s5p_gpio_bank mp2_8;
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struct s5p_gpio_bank res1[48];
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struct s5p_gpio_bank h0;
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struct s5p_gpio_bank h1;
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struct s5p_gpio_bank h2;
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struct s5p_gpio_bank h3;
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};
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/* functions */
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void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
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void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
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void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
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void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
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unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
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void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
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void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
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void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
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/* GPIO pins per bank */
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#define GPIO_PER_BANK 8
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static inline unsigned int s5p_gpio_base(int nr)
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{
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return S5PC110_GPIO_BASE;
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}
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static inline unsigned int s5p_gpio_part_max(int nr)
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{
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return 0;
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}
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#define s5pc110_gpio_get_nr(bank, pin) \
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((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
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- S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
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* GPIO_PER_BANK) + pin)
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#endif
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/* Pin configurations */
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#define GPIO_INPUT 0x0
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#define GPIO_OUTPUT 0x1
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#define GPIO_IRQ 0xf
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#define GPIO_FUNC(x) (x)
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/* Pull mode */
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#define GPIO_PULL_NONE 0x0
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#define GPIO_PULL_DOWN 0x1
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#define GPIO_PULL_UP 0x2
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/* Drive Strength level */
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#define GPIO_DRV_1X 0x0
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#define GPIO_DRV_3X 0x1
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#define GPIO_DRV_2X 0x2
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#define GPIO_DRV_4X 0x3
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#define GPIO_DRV_FAST 0x0
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#define GPIO_DRV_SLOW 0x1
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#endif
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