upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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69 lines
1.3 KiB
69 lines
1.3 KiB
/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SPR_GPT_H
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#define _SPR_GPT_H
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struct gpt_regs {
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u8 reserved[0x80];
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u32 control;
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u32 status;
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u32 compare;
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u32 count;
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u32 capture_re;
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u32 capture_fe;
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};
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/*
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* TIMER_CONTROL register settings
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*/
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#define GPT_PRESCALER_MASK 0x000F
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#define GPT_PRESCALER_1 0x0000
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#define GPT_PRESCALER_2 0x0001
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#define GPT_PRESCALER_4 0x0002
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#define GPT_PRESCALER_8 0x0003
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#define GPT_PRESCALER_16 0x0004
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#define GPT_PRESCALER_32 0x0005
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#define GPT_PRESCALER_64 0x0006
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#define GPT_PRESCALER_128 0x0007
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#define GPT_PRESCALER_256 0x0008
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#define GPT_MODE_SINGLE_SHOT 0x0010
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#define GPT_MODE_AUTO_RELOAD 0x0000
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#define GPT_ENABLE 0x0020
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#define GPT_CAPT_MODE_MASK 0x00C0
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#define GPT_CAPT_MODE_NONE 0x0000
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#define GPT_CAPT_MODE_RE 0x0040
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#define GPT_CAPT_MODE_FE 0x0080
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#define GPT_CAPT_MODE_BOTH 0x00C0
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#define GPT_INT_MATCH 0x0100
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#define GPT_INT_FE 0x0200
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#define GPT_INT_RE 0x0400
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/*
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* TIMER_STATUS register settings
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*/
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#define GPT_STS_MATCH 0x0001
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#define GPT_STS_FE 0x0002
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#define GPT_STS_RE 0x0004
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/*
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* TIMER_COMPARE register settings
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*/
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#define GPT_FREE_RUNNING 0xFFFF
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/* Timer, HZ specific defines */
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#define CONFIG_SPEAR_HZ 1000
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#define CONFIG_SPEAR_HZ_CLOCK 8300000
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#endif
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