upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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137 lines
4.0 KiB
137 lines
4.0 KiB
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* Copyright (c) 2013 NVIDIA Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA_USB_H_
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#define _TEGRA_USB_H_
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/* USB1_LEGACY_CTRL */
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#define USB1_NO_LEGACY_MODE 1
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#define VBUS_SENSE_CTL_SHIFT 1
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#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
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#define VBUS_SENSE_CTL_VBUS_WAKEUP 0
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#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
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#define VBUS_SENSE_CTL_AB_SESS_VLD 2
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#define VBUS_SENSE_CTL_A_SESS_VLD 3
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/* USBx_IF_USB_SUSP_CTRL_0 */
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#define UTMIP_PHY_ENB (1 << 12)
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#define UTMIP_RESET (1 << 11)
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#define USB_PHY_CLK_VALID (1 << 7)
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#define USB_SUSP_CLR (1 << 5)
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/* USB2_IF_USB_SUSP_CTRL_0 */
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#define ULPI_PHY_ENB (1 << 13)
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/* USBx_UTMIP_MISC_CFG0 */
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#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
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/* USBx_UTMIP_MISC_CFG1 */
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#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
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#define UTMIP_PLLU_STABLE_COUNT_MASK \
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(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
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#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
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#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
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(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
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#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
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/* USBx_UTMIP_PLL_CFG1_0 */
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#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
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#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
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(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
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#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
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#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
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/* USBx_UTMIP_BIAS_CFG0_0 */
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#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
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#define UTMIP_OTGPD (1 << 11)
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#define UTMIP_BIASPD (1 << 10)
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#define UTMIP_HSDISCON_LEVEL_SHIFT 2
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#define UTMIP_HSDISCON_LEVEL_MASK \
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(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
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#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
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#define UTMIP_HSSQUELCH_LEVEL_MASK \
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(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
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/* USBx_UTMIP_BIAS_CFG1_0 */
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#define UTMIP_FORCE_PDTRK_POWERDOWN 1
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#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
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#define UTMIP_BIAS_PDTRK_COUNT_MASK \
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(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
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/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
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#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
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#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
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/* USBx_UTMIP_TX_CFG0_0 */
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#define UTMIP_FS_PREAMBLE_J (1 << 19)
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/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
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#define UTMIP_PD_CHRG 1
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/* USBx_UTMIP_SPARE_CFG0_0 */
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#define FUSE_SETUP_SEL (1 << 3)
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/* USBx_UTMIP_HSRX_CFG0_0 */
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#define UTMIP_IDLE_WAIT_SHIFT 15
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#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
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#define UTMIP_ELASTIC_LIMIT_SHIFT 10
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#define UTMIP_ELASTIC_LIMIT_MASK \
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(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
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/* USBx_UTMIP_HSRX_CFG1_0 */
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#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
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#define UTMIP_HS_SYNC_START_DLY_MASK \
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(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
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/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
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#define IC_ENB1 (1 << 3)
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/* PORTSC1, USB1, defined for Tegra20 */
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#define PTS1_SHIFT 31
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#define PTS1_MASK (1 << PTS1_SHIFT)
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#define STS1 (1 << 30)
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#define PTS_UTMI 0
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#define PTS_RESERVED 1
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#define PTS_ULPI 2
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#define PTS_ICUSB_SER 3
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#define PTS_HSIC 4
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/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
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#define WKOC (1 << 22)
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#define WKDS (1 << 21)
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#define WKCN (1 << 20)
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/* USBx_UTMIP_XCVR_CFG0_0 */
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#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
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#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
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#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
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#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
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#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
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#define UTMIP_XCVR_HSSLEW_MSB_MASK \
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(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
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#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
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#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
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#define UTMIP_XCVR_SETUP_SHIFT 0
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#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
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/* USBx_UTMIP_XCVR_CFG1_0 */
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#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
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#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
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(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
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#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
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#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
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#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
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/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
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#define VBUS_VLD_STS (1 << 26)
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/* Setup USB on the board */
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int usb_process_devicetree(const void *blob);
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#endif /* _TEGRA_USB_H_ */
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