upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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213 lines
5.2 KiB
213 lines
5.2 KiB
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
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#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
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#ifndef __ASSEMBLY__
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/* Clock Controller Module (CCM) */
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struct ccm_reg {
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u32 ccr;
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u32 csr;
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u32 ccsr;
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u32 cacrr;
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u32 cscmr1;
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u32 cscdr1;
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u32 cscdr2;
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u32 cscdr3;
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u32 cscmr2;
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u32 cscdr4;
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u32 ctor;
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u32 clpcr;
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u32 cisr;
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u32 cimr;
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u32 ccosr;
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u32 cgpr;
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u32 ccgr0;
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u32 ccgr1;
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u32 ccgr2;
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u32 ccgr3;
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u32 ccgr4;
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u32 ccgr5;
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u32 ccgr6;
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u32 ccgr7;
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u32 ccgr8;
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u32 ccgr9;
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u32 ccgr10;
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u32 ccgr11;
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u32 cmeor0;
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u32 cmeor1;
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u32 cmeor2;
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u32 cmeor3;
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u32 cmeor4;
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u32 cmeor5;
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u32 cppdsr;
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u32 ccowr;
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u32 ccpgr0;
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u32 ccpgr1;
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u32 ccpgr2;
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u32 ccpgr3;
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};
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/* Analog components control digital interface (ANADIG) */
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struct anadig_reg {
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u32 pll3_ctrl;
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u32 resv0[3];
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u32 pll7_ctrl;
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u32 resv1[3];
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u32 pll2_ctrl;
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u32 resv2[3];
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u32 pll2_ss;
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u32 resv3[3];
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u32 pll2_num;
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u32 resv4[3];
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u32 pll2_denom;
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u32 resv5[3];
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u32 pll4_ctrl;
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u32 resv6[3];
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u32 pll4_num;
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u32 resv7[3];
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u32 pll4_denom;
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u32 pll6_ctrl;
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u32 resv8[3];
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u32 pll6_num;
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u32 resv9[3];
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u32 pll6_denom;
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u32 resv10[3];
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u32 pll5_ctrl;
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u32 resv11[3];
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u32 pll3_pfd;
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u32 resv12[3];
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u32 pll2_pfd;
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u32 resv13[3];
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u32 reg_1p1;
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u32 resv14[3];
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u32 reg_3p0;
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u32 resv15[3];
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u32 reg_2p5;
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u32 resv16[7];
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u32 ana_misc0;
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u32 resv17[3];
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u32 ana_misc1;
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u32 resv18[63];
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u32 anadig_digprog;
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u32 resv19[3];
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u32 pll1_ctrl;
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u32 resv20[3];
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u32 pll1_ss;
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u32 resv21[3];
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u32 pll1_num;
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u32 resv22[3];
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u32 pll1_denom;
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u32 resv23[3];
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u32 pll1_pdf;
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u32 resv24[3];
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u32 pll_lock;
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};
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#endif
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#define CCM_CCR_FIRC_EN (1 << 16)
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#define CCM_CCR_OSCNT_MASK 0xff
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#define CCM_CCR_OSCNT(v) ((v) & 0xff)
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#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
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#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
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#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
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#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
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#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
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#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
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#define CCM_CCSR_PLL2_PFD4_EN (1 << 15)
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#define CCM_CCSR_PLL2_PFD3_EN (1 << 14)
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#define CCM_CCSR_PLL2_PFD2_EN (1 << 13)
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#define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
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#define CCM_CCSR_PLL1_PFD4_EN (1 << 11)
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#define CCM_CCSR_PLL1_PFD3_EN (1 << 10)
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#define CCM_CCSR_PLL1_PFD2_EN (1 << 9)
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#define CCM_CCSR_PLL1_PFD1_EN (1 << 8)
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#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6)
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#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5)
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#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
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#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
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#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
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#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
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#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
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#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
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#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
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#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
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#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3)
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#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
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#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
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#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
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#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
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#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
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#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
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#define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
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#define CCM_CSCDR2_ESDHC1_EN (1 << 29)
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#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
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#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
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#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
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#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
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#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
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#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
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#define CCM_REG_CTRL_MASK 0xffffffff
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#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
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#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
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#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
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#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
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#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
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#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
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#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22)
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#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
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#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
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#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
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#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
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#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
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#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
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#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
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#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
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#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
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#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
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#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
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#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
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#define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL2_CTRL_DIV_SELECT 1
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#define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL1_CTRL_DIV_SELECT 1
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#define FASE_CLK_FREQ 24000000
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#define SLOW_CLK_FREQ 32000
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#define PLL1_PFD1_FREQ 500000000
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#define PLL1_PFD2_FREQ 452000000
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#define PLL1_PFD3_FREQ 396000000
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#define PLL1_PFD4_FREQ 528000000
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#define PLL1_MAIN_FREQ 528000000
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#define PLL2_PFD1_FREQ 500000000
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#define PLL2_PFD2_FREQ 396000000
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#define PLL2_PFD3_FREQ 339000000
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#define PLL2_PFD4_FREQ 413000000
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#define PLL2_MAIN_FREQ 528000000
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#define PLL3_MAIN_FREQ 480000000
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#define PLL3_PFD3_FREQ 298000000
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#define PLL5_MAIN_FREQ 500000000
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#define ENET_EXTERNAL_CLK 50000000
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#define AUDIO_EXTERNAL_CLK 24576000
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#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */
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