upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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90 lines
2.3 KiB
90 lines
2.3 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* hardware_am43xx.h
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*
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* AM43xx hardware specific header
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#ifndef __AM43XX_HARDWARE_AM43XX_H
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#define __AM43XX_HARDWARE_AM43XX_H
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/* Module base addresses */
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/* L3 Fast Configuration Bandwidth Limiter Base Address */
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#define L3F_CFG_BWLIMITER 0x44005200
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/* UART Base Address */
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#define UART0_BASE 0x44E09000
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/* GPIO Base address */
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#define GPIO2_BASE 0x481AC000
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/* Watchdog Timer */
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#define WDT_BASE 0x44E35000
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/* Control Module Base Address */
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#define CTRL_BASE 0x44E10000
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#define CTRL_DEVICE_BASE 0x44E10600
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/* PRCM Base Address */
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#define PRCM_BASE 0x44DF0000
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#define CM_WKUP 0x44DF2800
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#define CM_PER 0x44DF8800
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#define CM_DPLL 0x44DF4200
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#define CM_RTC 0x44DF8500
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#define PRM_RSTCTRL (PRCM_BASE + 0x4000)
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#define PRM_RSTST (PRM_RSTCTRL + 4)
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/* VTP Base address */
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#define VTP0_CTRL_ADDR 0x44E10E0C
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#define VTP1_CTRL_ADDR 0x48140E10
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/* USB CTRL Base Address */
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#define USB1_CTRL 0x44e10628
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#define USB1_CTRL_CM_PWRDN BIT(0)
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#define USB1_CTRL_OTG_PWRDN BIT(1)
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/* DDR Base address */
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#define DDR_PHY_CMD_ADDR 0x44E12000
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#define DDR_PHY_DATA_ADDR 0x44E120C8
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#define DDR_PHY_CMD_ADDR2 0x47C0C800
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#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
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#define DDR_DATA_REGS_NR 2
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/* CPSW Config space */
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#define CPSW_MDIO_BASE 0x4A101000
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/* RTC base address */
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#define RTC_BASE 0x44E3E000
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/* USB OTG */
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#define USB_OTG_SS1_BASE 0x48390000
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#define USB_OTG_SS1_GLUE_BASE 0x48380000
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#define USB2_PHY1_POWER 0x44E10620
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#define USB_OTG_SS2_BASE 0x483D0000
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#define USB_OTG_SS2_GLUE_BASE 0x483C0000
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#define USB2_PHY2_POWER 0x44E10628
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/* USB Clock Control */
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#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
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#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
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#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1)
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#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
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#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
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#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
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#define USBPHYOCPSCP_MODULE_EN (1 << 1)
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#define CM_DEVICE_INST 0x44df4100
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#define PRM_DEVICE_INST 0x44df4000
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#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
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#define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
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/* EDMA3 Base Address */
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#define EDMA3_BASE 0x49000000
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#endif /* __AM43XX_HARDWARE_AM43XX_H */
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