upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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398 lines
14 KiB
398 lines
14 KiB
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_IC_SC520_H_
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#define _ASM_IC_SC520_H_ 1
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#ifndef __ASSEMBLY__
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void init_sc520(void);
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unsigned long init_sc520_dram(void);
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void sc520_udelay(unsigned long usec);
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/* Memory mapped configuration registers */
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typedef struct sc520_mmcr {
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u16 revid; /* ElanSC520 microcontroller revision id */
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u8 cpuctl; /* am5x86 CPU control */
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u8 pad_0x003[0x0d];
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u8 drcctl; /* SDRAM control */
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u8 pad_0x011[0x01];
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u8 drctmctl; /* SDRAM timing control */
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u8 pad_0x013[0x01];
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u16 drccfg; /* SDRAM bank configuration*/
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u8 pad_0x016[0x02];
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u32 drcbendadr; /* SDRAM bank 0-3 ending address*/
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u8 pad_0x01c[0x04];
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u8 eccctl; /* ECC control */
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u8 eccsta; /* ECC status */
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u8 eccckbpos; /* ECC check bit position */
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u8 ecccktest; /* ECC Check Code Test */
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u32 eccsbadd; /* ECC single-bit error address */
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u32 eccmbadd; /* ECC multi-bit error address */
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u8 pad_0x02c[0x14];
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u8 dbctl; /* SDRAM buffer control */
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u8 pad_0x041[0x0f];
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u16 bootcsctl; /* /BOOTCS control */
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u8 pad_0x052[0x02];
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u16 romcs1ctl; /* /ROMCS1 control */
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u16 romcs2ctl; /* /ROMCS2 control */
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u8 pad_0x058[0x08];
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u16 hbctl; /* host bridge control */
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u16 hbtgtirqctl; /* host bridge target interrupt control */
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u16 hbtgtirqsta; /* host bridge target interrupt status */
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u16 hbmstirqctl; /* host bridge target interrupt control */
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u16 hbmstirqsta; /* host bridge master interrupt status */
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u8 pad_0x06a[0x02];
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u32 mstintadd; /* host bridge master interrupt address */
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u8 sysarbctl; /* system arbiter control */
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u8 pciarbsta; /* PCI bus arbiter status */
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u16 sysarbmenb; /* system arbiter master enable */
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u32 arbprictl; /* arbiter priority control */
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u8 pad_0x078[0x08];
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u8 adddecctl; /* address decode control */
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u8 pad_0x081[0x01];
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u16 wpvsta; /* write-protect violation status */
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u8 pad_0x084[0x04];
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u32 par[16]; /* programmable address regions */
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u8 pad_0x0c8[0x0b38];
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u8 gpecho; /* GP echo mode */
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u8 gpcsdw; /* GP chip select data width */
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u16 gpcsqual; /* GP chip select qualification */
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u8 pad_0xc04[0x4];
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u8 gpcsrt; /* GP chip select recovery time */
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u8 gpcspw; /* GP chip select pulse width */
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u8 gpcsoff; /* GP chip select offset */
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u8 gprdw; /* GP read pulse width */
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u8 gprdoff; /* GP read offset */
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u8 gpwrw; /* GP write pulse width */
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u8 gpwroff; /* GP write offset */
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u8 gpalew; /* GP ale pulse width */
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u8 gpaleoff; /* GP ale offset */
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u8 pad_0xc11[0x0f];
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u16 piopfs15_0; /* PIO15-PIO0 pin function select */
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u16 piopfs31_16; /* PIO31-PIO16 pin function select */
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u8 cspfs; /* chip select pin function select */
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u8 pad_0xc25[0x01];
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u8 clksel; /* clock select */
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u8 pad_0xc27[0x01];
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u16 dsctl; /* drive strength control */
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u16 piodir15_0; /* PIO15-PIO0 direction */
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u16 piodir31_16; /* PIO31-PIO16 direction */
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u8 pad_0xc2e[0x02];
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u16 piodata15_0 ; /* PIO15-PIO0 data */
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u16 piodata31_16; /* PIO31-PIO16 data */
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u16 pioset15_0; /* PIO15-PIO0 set */
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u16 pioset31_16; /* PIO31-PIO16 set */
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u16 pioclr15_0; /* PIO15-PIO0 clear */
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u16 pioclr31_16; /* PIO31-PIO16 clear */
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u8 pad_0xc3c[0x24];
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u16 swtmrmilli; /* software timer millisecond count */
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u16 swtmrmicro; /* software timer microsecond count */
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u8 swtmrcfg; /* software timer configuration */
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u8 pad_0xc65[0x0b];
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u8 gptmrsta; /* GP timers status register */
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u8 pad_0xc71;
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u16 gptmr0ctl; /* GP timer 0 mode/control */
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u16 gptmr0cnt; /* GP timer 0 count */
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u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */
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u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */
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u16 gptmr1ctl; /* GP timer 1 mode/control */
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u16 gptmr1cnt; /* GP timer 1 count */
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u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */
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u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/
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u16 gptmr2ctl; /* GP timer 2 mode/control */
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u16 gptmr2cnt; /* GP timer 2 count */
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u8 pad_0xc86[0x08];
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u16 gptmr2maxcmpa; /* GP timer 2 maxcount compare A */
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u8 pad_0xc90[0x20];
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u16 wdtmrctl; /* watchdog timer control */
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u16 wdtmrcntl; /* watchdog timer count low */
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u16 wdtmrcnth; /* watchdog timer count high */
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u8 pad_0xcb6[0x0a];
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u8 uart1ctl; /* UART 1 general control */
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u8 uart1sta; /* UART 1 general status */
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u8 uart1fcrshad; /* UART 1 FIFO control shadow */
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u8 pad_0xcc3[0x01];
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u8 uart2ctl; /* UART 2 general control */
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u8 uart2sta; /* UART 2 general status */
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u8 uart2fcrshad; /* UART 2 FIFO control shadow */
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u8 pad_0xcc7[0x09];
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u8 ssictl; /* SSI control */
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u8 ssixmit; /* SSI transmit */
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u8 ssicmd; /* SSI command */
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u8 ssista; /* SSI status */
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u8 ssircv; /* SSI receive */
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u8 pad_0xcd5[0x2b];
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u8 picicr; /* interrupt control */
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u8 pad_0xd01[0x01];
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u8 pic_mode[3]; /* PIC interrupt mode */
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u8 pad_0xd05[0x03];
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u16 swint16_1; /* software interrupt 16-1 control */
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u8 swint22_17; /* software interrupt 22-17/NMI control */
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u8 pad_0xd0b[0x05];
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u16 intpinpol; /* interrupt pin polarity */
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u8 pad_0xd12[0x02];
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u16 pcihostmap; /* PCI host bridge interrupt mapping */
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u8 pad_0xd16[0x02];
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u16 eccmap; /* ECC interrupt mapping */
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u8 gp_tmr_int_map[3]; /* GP timer interrupt mapping */
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u8 pad_0xd1d[0x03];
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u8 pit_int_map[3]; /* PIT interrupt mapping */
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u8 pad_0xd23[0x05];
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u8 uart_int_map[2]; /* UART interrupt mapping */
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u8 pad_0xd2a[0x06];
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u8 pci_int_map[4]; /* PCI interrupt mapping (A through D)*/
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u8 pad_0xd34[0x0c];
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u8 dmabcintmap; /* DMA buffer chaining interrupt mapping */
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u8 ssimap; /* SSI interrupt mapping register */
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u8 wdtmap; /* watchdog timer interrupt mapping */
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u8 rtcmap; /* RTC interrupt mapping register */
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u8 wpvmap; /* write-protect interrupt mapping */
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u8 icemap; /* AMDebug JTAG Rx/Tx interrupt mapping */
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u8 ferrmap; /* floating point error interrupt mapping */
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u8 pad_0xd47[0x09];
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u8 gp_int_map[11]; /* GP IRQ interrupt mapping */
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u8 pad_0xd5b[0x15];
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u8 sysinfo; /* system board information */
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u8 pad_0xd71[0x01];
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u8 rescfg; /* reset configuration */
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u8 pad_0xd73[0x01];
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u8 ressta; /* reset status */
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u8 pad_0xd75[0x0b];
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u8 gpdmactl; /* GP-DMA Control */
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u8 gpdmammio; /* GP-DMA memory-mapped I/O */
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u16 gpdmaextchmapa; /* GP-DMA resource channel map a */
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u16 gpdmaextchmapb; /* GP-DMA resource channel map b */
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u8 gp_dma_ext_pg_0; /* GP-DMA channel extended page 0 */
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u8 gp_dma_ext_pg_1; /* GP-DMA channel extended page 0 */
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u8 gp_dma_ext_pg_2; /* GP-DMA channel extended page 0 */
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u8 gp_dma_ext_pg_3; /* GP-DMA channel extended page 0 */
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u8 gp_dma_ext_pg_5; /* GP-DMA channel extended page 0 */
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u8 gp_dma_ext_pg_6; /* GP-DMA channel extended page 0 */
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u8 gp_dma_ext_pg_7; /* GP-DMA channel extended page 0 */
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u8 pad_0xd8d[0x03];
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u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */
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u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */
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u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */
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u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */
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u8 pad_0xd94[0x4];
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u8 gpdmabcctl; /* buffer chaining control */
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u8 gpdmabcsta; /* buffer chaining status */
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u8 gpdmabsintenb; /* buffer chaining interrupt enable */
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u8 gpdmabcval; /* buffer chaining valid */
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u8 pad_0xd9c[0x04];
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u16 gpdmanxtaddl3; /* GP-DMA channel 3 next address low */
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u16 gpdmanxtaddh3; /* GP-DMA channel 3 next address high */
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u16 gpdmanxtaddl5; /* GP-DMA channel 5 next address low */
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u16 gpdmanxtaddh5; /* GP-DMA channel 5 next address high */
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u16 gpdmanxtaddl6; /* GP-DMA channel 6 next address low */
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u16 gpdmanxtaddh6; /* GP-DMA channel 6 next address high */
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u16 gpdmanxtaddl7; /* GP-DMA channel 7 next address low */
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u16 gpdmanxtaddh7; /* GP-DMA channel 7 next address high */
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u16 gpdmanxttcl3; /* GP-DMA channel 3 next transfer count low */
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u16 gpdmanxttch3; /* GP-DMA channel 3 next transfer count high */
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u16 gpdmanxttcl5; /* GP-DMA channel 5 next transfer count low */
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u16 gpdmanxttch5; /* GP-DMA channel 5 next transfer count high */
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u16 gpdmanxttcl6; /* GP-DMA channel 6 next transfer count low */
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u16 gpdmanxttch6; /* GP-DMA channel 6 next transfer count high */
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u16 gpdmanxttcl7; /* GP-DMA channel 7 next transfer count low */
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u16 gpdmanxttch7; /* GP-DMA channel 7 next transfer count high */
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u8 pad_0xdc0[0x0240];
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} sc520_mmcr_t;
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extern sc520_mmcr_t *sc520_mmcr;
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#endif
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/* Memory Mapped Control Registers (MMCR) Base Address */
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#define SC520_MMCR_BASE 0xfffef000
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/* MMCR Addresses (required for assembler code) */
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#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010)
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#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012)
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#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014)
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#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018)
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#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020)
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#define SC520_DBCTL (SC520_MMCR_BASE + 0x040)
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#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18)
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#define SC520_PAR0 (SC520_MMCR_BASE + 0x088)
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#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1))
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#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2))
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#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3))
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#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4))
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#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5))
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#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6))
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#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7))
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#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8))
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#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9))
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#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10))
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#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11))
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#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12))
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#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13))
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#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14))
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#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))
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/*
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* PARs for maximum allowable 256MB of SDRAM @ 0x00000000
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* Two PARs are required due to maximum PAR size of 128MB
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* These are used in the SDRAM sizing code to disable caching
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*
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* 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
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* 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800
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* \ / | | | | \----+----/ \-----+------/
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* | | | | | | +---------- Start at 0x00000000
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* | | | | | | 0x08000000
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* | | | | | +----------------------- 128MB Region Size
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* | | | | | ((2047 + 1) * 64kB)
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* | | | | +------------------------------ 64kB Page Size
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* | | | +-------------------------------- Writes Enabled
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* | | +---------------------------------- Caching Enabled
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* | +------------------------------------ Execution Enabled
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* +--------------------------------------- SDRAM
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*/
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#define SC520_SDRAM1_PAR 0xe3ffc000
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#define SC520_SDRAM2_PAR 0xe3ffc800
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#define SC520_PAR_WRITE_DIS 0x04000000
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#define SC520_PAR_CACHE_DIS 0x08000000
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#define SC520_PAR_EXEC_DIS 0x10000000
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/*
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* Programmable Address Regions to cover 256MB SDRAM (Maximum supported)
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* required for DRAM sizing code
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*/
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/* MMCR Register bits (not all of them :) ) */
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/* SSI Stuff */
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#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */
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#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */
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#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */
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#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */
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#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */
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#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */
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#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */
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#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */
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#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */
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#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */
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#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */
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#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */
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#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */
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#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */
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#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */
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#define SSISTA_BSY 0x02 /* SSI Busy */
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#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */
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/* BITS for SC520_ADDDECCTL: */
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#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */
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#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */
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#define RTC_DIS 0x04 /* RTC Disable */
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#define UART2_DIS 0x02 /* UART2 Disable */
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#define UART1_DIS 0x01 /* UART1 Disable */
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/*
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* Defines used for SDRAM Sizing (number of columns and rows)
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* Refer to section 10.6.4 - SDRAM Sizing Algorithm in the
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* Elan SC520 Microcontroller User's Manual (Order #22004B)
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*/
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#define CACHELINESZ 0x00000010
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#define COL11_ADR 0x0e001e00
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#define COL10_ADR 0x0e000e00
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#define COL09_ADR 0x0e000600
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#define COL08_ADR 0x0e000200
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#define COL11_DATA 0x0b0b0b0b
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#define COL10_DATA 0x0a0a0a0a
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#define COL09_DATA 0x09090909
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#define COL08_DATA 0x08080808
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#define ROW14_ADR 0x0f000000
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#define ROW13_ADR 0x07000000
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#define ROW12_ADR 0x03000000
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#define ROW11_ADR 0x01000000
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#define ROW10_ADR 0x00000000
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#define ROW14_DATA 0x3f3f3f3f
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#define ROW13_DATA 0x1f1f1f1f
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#define ROW12_DATA 0x0f0f0f0f
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#define ROW11_DATA 0x07070707
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#define ROW10_DATA 0xaaaaaaaa
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/* 0x28000000 - 0x3fffffff is used by the flash banks */
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/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
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/* priority numbers used for interrupt channel mappings */
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#define SC520_IRQ_DISABLED 0
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#define SC520_IRQ0 1
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#define SC520_IRQ1 2
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#define SC520_IRQ2 4 /* same as IRQ9 */
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#define SC520_IRQ3 11
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#define SC520_IRQ4 12
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#define SC520_IRQ5 13
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#define SC520_IRQ6 21
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#define SC520_IRQ7 22
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#define SC520_IRQ8 3
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#define SC520_IRQ9 4
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#define SC520_IRQ10 5
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#define SC520_IRQ11 6
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#define SC520_IRQ12 7
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#define SC520_IRQ13 8
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#define SC520_IRQ14 9
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#define SC520_IRQ15 10
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#endif
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